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Microprocessor Error Recovery Methodology

IP.com Disclosure Number: IPCOM000060228D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kruppa, RW: AUTHOR

Abstract

This article sets forth a technique that causes a software reset as a result of a processor "hang" condition or an inappropriate "jump" to a wrong address in microcode. The "hang" and/or "jump" condition may result from the microprocessor getting lost due to ESD (electrostatic discharge), noise or power line transients (PLT) glitches. In this error recovery routine, the primary concern is that of detecting that an error has occurred. The reaction to the detection is of secondary concern. This routine requires that the software be well structured and, more specifically, that each I/O function, such as wire fire routines, paper advances and transport motion, for example, be contained in a well-defined block of code, as shown in Fig. 1. At the beginning of each block of code, the following must be executed: 1.

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Microprocessor Error Recovery Methodology

This article sets forth a technique that causes a software reset as a result of a processor "hang" condition or an inappropriate "jump" to a wrong address in microcode. The "hang" and/or "jump" condition may result from the microprocessor getting lost due to ESD (electrostatic discharge), noise or power line transients (PLT) glitches. In this error recovery routine, the primary concern is that of detecting that an error has occurred. The reaction to the detection is of secondary concern. This routine requires that the software be well structured and, more specifically, that each I/O function, such as wire fire routines, paper advances and transport motion, for example, be contained in a well-defined block of code, as shown in Fig. 1. At the beginning of each block of code, the following must be executed: 1. Place in the RAM a 7-bit (plus parity) code which is unique to each I/O function. 2. Start a processor timer, set at the time required to process the longest path through a block of code. The applications code would follow next. At the end of each block of code, a check of the 7-bit function code (plus parity) is made. If a match is not made with that stored in the RAM, the processor is lost and an error recovery routine is now executed. Likewise, if the timer times out, the processor is in a loop or has jumped to another program area. Again, an error routine is executed (Fig. 2). Obviously, if the processor ceases to...