Browse Prior Art Database

Processor Communication Interface

IP.com Disclosure Number: IPCOM000060245D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Kessler, SL: AUTHOR

Abstract

An interrupt-driven interface allows two central processing units (CPUs) having differing execution speeds to communicate with each other. The interface (Fig. 1) consists of an address bus 1, a data bus 2, a control bus 3, interrupt lines 4, and a shared memory 5 that is attached to the bus. Two unidirectional interrupt lines 4 allow each processor to send an interrupt signal to the other processor. The memory 5 is segmented into an area for control information and an area for data. The control section is used by one CPU to send instructions to the other CPU. The transfer of data between processors is accomplished after the data is placed into the data area of the common memory 5. The communication algorithm contains the transmission routine (Fig. 2A) and the receiving routine (Fig. 2B).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Processor Communication Interface

An interrupt-driven interface allows two central processing units (CPUs) having differing execution speeds to communicate with each other. The interface (Fig.
1) consists of an address bus 1, a data bus 2, a control bus 3, interrupt lines 4, and a shared memory 5 that is attached to the bus. Two unidirectional interrupt lines 4 allow each processor to send an interrupt signal to the other processor. The memory 5 is segmented into an area for control information and an area for data. The control section is used by one CPU to send instructions to the other CPU. The transfer of data between processors is accomplished after the data is placed into the data area of the common memory 5. The communication algorithm contains the transmission routine (Fig. 2A) and the receiving routine (Fig. 2B). Processor communication is initiated by first storing data in the shared memory 5 (Fig. 1), clearing the response field in the control space, and then setting a request field with the desired command. An interrupt is then sent to the other processor. When the second CPU receives an interrupt, it reads the request field to determine what the first CPU wants. It then reads the data space, if required, sets up the response field, and sends an interrupt back to the first processor. When the first processor receives the interrupt from the second processor, it reads the response field in the control space to determine the outcome of the previous reques...