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Substrate Bias Generator Utilizing Hole Extraction for Latch-Up Prevention of CMOS Circuitry

IP.com Disclosure Number: IPCOM000060253D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dovek, MM: AUTHOR [+2]

Abstract

This article describes a structure designed to eliminate CMOS circuit susceptibility to latch-up due to substrate bias generators. The structure includes a substrate bias generator which utilizes hole extraction to bias the p-type substrate to a negative potential in an n-well CMOS technology and hence will avoid circuitry latch-up. Substrate generators designed completely in n-channel FET devices can cause latch-up if utilized with CMOS circuitry. This is because, in the n-channel design, some of the n-diffusions in the generator can be temporarily at a potential lower (more negative) than that of the substrate. This will forward bias these junctions, resulting in electron injection into the substrate and eventually latch-up of the neighboring CMOS circuitry.

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Substrate Bias Generator Utilizing Hole Extraction for Latch-Up Prevention of CMOS Circuitry

This article describes a structure designed to eliminate CMOS circuit susceptibility to latch-up due to substrate bias generators. The structure includes a substrate bias generator which utilizes hole extraction to bias the p-type substrate to a negative potential in an n-well CMOS technology and hence will avoid circuitry latch-up. Substrate generators designed completely in n-channel FET devices can cause latch-up if utilized with CMOS circuitry. This is because, in the n-channel design, some of the n-diffusions in the generator can be temporarily at a potential lower (more negative) than that of the substrate. This will forward bias these junctions, resulting in electron injection into the substrate and eventually latch-up of the neighboring CMOS circuitry. A solution to this problem is to guard ring the substrate generator utilizing a deep n-well connected to the most positive voltage available. This solution, though simple, reduces the efficiency of the substrate bias generator by extracting the very same electrons which bias the substrate negative. In the structure presented in this article the design of the substrate bias generator depends on hole extraction from the p- type substrate of an n-well CMOS technology to bias it negative. This will avoid the electron injection problem mentioned above and hence circuitry latch-up. The substrate bias generator is designed in the CMOS- II technology. It consists of a nine-stage ring oscillator that serves as a clock and a pump that uses capacitive coupling between two nodes to pump the substrate to a negative voltage. The ring oscillator (Fig. 1) has nine stages of inve...