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Wire Matrix

IP.com Disclosure Number: IPCOM000060292D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Long, GB: AUTHOR [+4]

Abstract

A wiring arrangement that can be used in the design of CMOS chips is described. In the design of chips there are typically large areas containing only wiring, no circuits. The wiring in these areas can be replaced by a Wire Matrix (WM). The reduction in size is accomplished by using both first- and second-level metal along one axis while using diffusion along the other axis. This wiring has a large increase in density over second metal and a smaller increase over first metal. The major incentive for using the WM is wiring pitch. Traditional wiring consists of busses composed of either first or second metal lines in a given wiring dimension. For many chips, second metal has been used for most of the horizontal data flow, while first metal is used for the vertical data flow.

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Wire Matrix

A wiring arrangement that can be used in the design of CMOS chips is described. In the design of chips there are typically large areas containing only wiring, no circuits. The wiring in these areas can be replaced by a Wire Matrix (WM). The reduction in size is accomplished by using both first- and second- level metal along one axis while using diffusion along the other axis. This wiring has a large increase in density over second metal and a smaller increase over first metal. The major incentive for using the WM is wiring pitch. Traditional wiring consists of busses composed of either first or second metal lines in a given wiring dimension. For many chips, second metal has been used for most of the horizontal data flow, while first metal is used for the vertical data flow. In the design of chips there are typically one or more circuit columns. A circuit column can be a stack of registers, multiplexers, or logic macros. In cases when there is more than one column, an area needs to be allocated so that communication between the two columns can take place. This area can be allocated as one large unit or as multiple smaller units. For WM application it is desirable to have these wiring areas as consolidated as possible. Doing this creates centralized areas on the chip for horizontal communication to take place. The horizontal wiring is generally done on second metal, and the vertical wiring on first metal. As chip size and function began to increase so did the amount of horizontal data communication. The WM, as shown in the figure, can reduce the area required for such wiring. The wiring done within the WM is on pitch in the range of 3.8 to
4.1 microns. When used to replace...