Browse Prior Art Database

Partial Polycrystalline Silicon-Filled Trench for VLSI

IP.com Disclosure Number: IPCOM000060322D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Kemlage, BM: AUTHOR [+2]

Abstract

Over-planarization may occur in polycrystalline silicon-filled trench (PST) isolation processes for VLSI (very large-scale integration) in semiconductor devices. This recesses the fill below the wafer surface and may expose epitaxy regions causing electrical shorts. In addition to N-epi shorting to the substrate, stress can result from oxidizing the filled poly-Si through poly-Si voids in the deep trench region. This article proposes a process for protecting the poly at appropriate steps so as to overcome these problems. Fig. 1 shows the various films on N-type epi 8 grown on p-type silicon substrate 3 by means of a standard PST (poly-silicon trench) process.

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Partial Polycrystalline Silicon-Filled Trench for VLSI

Over-planarization may occur in polycrystalline silicon-filled trench (PST) isolation processes for VLSI (very large-scale integration) in semiconductor devices. This recesses the fill below the wafer surface and may expose epitaxy regions causing electrical shorts. In addition to N-epi shorting to the substrate, stress can result from oxidizing the filled poly-Si through poly-Si voids in the deep trench region. This article proposes a process for protecting the poly at appropriate steps so as to overcome these problems. Fig. 1 shows the various films on N-type epi 8 grown on p-type silicon substrate 3 by means of a standard PST (poly-silicon trench) process.

The other layers are N+ 9, LPCVD (low pressure chemical vapor deposition) oxide 4, Si3N4 5, thermal oxide 6 and ROI (recessed oxide isolation) 7. A mutlilayer resist (MLR) structure for deep trench image definition is on top of the LPCVD oxide and consists of two PR (photoresist) layers 1 and an LTO (low temperature oxide) layer 2. In the next step the deep trench 11 (Fig. 2) is formed by RIE (Reactive Ion etch) of the oxide-Si3N4-oxide sandwich with CHF3 followed by a PR strip and then an RIE of the Si with CCl2F2 + N2 . The LPCVD oxide may have been etched down to 0.5 mm. Low temperature poly- Si 10 about 0.4 mm thick is then deposited and doped in situ .

A thin layer of CVD (chemical vapor deposition) nitride (about 500 Angstroms) 5 is deposited. The remaining deep trench is filled with LPCVD oxide (1 mm) 4. A...