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Universal Monitored Burn-In Test Technique for IBM Series/1 Input/Output Attachment Cards

IP.com Disclosure Number: IPCOM000060341D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Crouse, R: AUTHOR

Abstract

A technique is described whereby a circuit provides monitored burn-in capability to microprocessor-based IBM Series/1 (S/1) input/output (I/O) attachment cards. The technique provides for burn-in of cards not originally designed to support burn-in. Burn-in on the Series/1 attachment cards requires that the following two design requirements be made for any attachment intended for monitored burn-in testing: 1. The attachment microcode must sense the presence of a special burn-in indicator jumper on the attachment so as to re-execute the power-on micro-diagnostics on a continuing basis until the jumper is removed. 2. The attachment hardware must generate a "test good" logical transistor-transistor logic (TTL) signal for each successful pass through the card micro-diagnostics.

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Universal Monitored Burn-In Test Technique for IBM Series/1 Input/Output Attachment Cards

A technique is described whereby a circuit provides monitored burn-in capability to microprocessor-based IBM Series/1 (S/1) input/output (I/O) attachment cards. The technique provides for burn-in of cards not originally designed to support burn-in. Burn-in on the Series/1 attachment cards requires that the following two design requirements be made for any attachment intended for monitored burn-in testing: 1. The attachment microcode must sense the presence of a special burn-in indicator jumper on the attachment so as to re-execute the power-on micro-diagnostics on a continuing basis until the jumper is removed. 2. The attachment hardware must generate a "test good" logical transistor-transistor logic (TTL) signal for each successful pass through the card micro-diagnostics. The circuit takes advantage of the S/1 architecture which requires that, after a power-on reset, an I/O attachment remains in a "Busy After Reset" (BAR) state until the attachment microprocessor successfully executes its power-on micro- diagnostics. The circuit monitors the BAR condition so that when the BAR state turns on and then off, the power-on reset input of the attachment under test is activated. All microprocessor-based S/1 attachments are then forced to re- execute their micro-diagnostics, satisfying design requirement 1 above. After each successful on-to-off transition of the BAR state, the circuit generates a logical TTL level "test good" pulse. In the event that an attachment fails the micro-diagnostic test, the BAR state would remain on and the "test good" pulse would be discontinued, satisfying design requirement 2 above. The circuit, as shown in Fig....