Browse Prior Art Database

Reduced Coupled Noise Technique for Engineering Changes

IP.com Disclosure Number: IPCOM000060376D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Huang, CC: AUTHOR [+4]

Abstract

This article concerns a ground wire technique for reducing unwanted noise coupling or cross-talk between engineering changes (ECs) or repair wires used on high performance multilayer ceramic (MLC) modules. In addition, the impedance of the discrete wire net is controlled, reducing the effect of discontinuities on signal risetime. Printed, buried engineering change wires are currently located in wiring channels to allow for product repair and engineering changes on multilayer ceramic modules. Excessive noise coupling or cross-talk occurring on the discrete wire jumpers that run from chip EC pad to buried EC pad in such modules effectively limits their performance.

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Reduced Coupled Noise Technique for Engineering Changes

This article concerns a ground wire technique for reducing unwanted noise coupling or cross-talk between engineering changes (ECs) or repair wires used on high performance multilayer ceramic (MLC) modules. In addition, the impedance of the discrete wire net is controlled, reducing the effect of discontinuities on signal risetime. Printed, buried engineering change wires are currently located in wiring channels to allow for product repair and engineering changes on multilayer ceramic modules. Excessive noise coupling or cross-talk occurring on the discrete wire jumpers that run from chip EC pad to buried EC pad in such modules effectively limits their performance. The disclosed technique calls for the placement of additional ground wires adjacent and parallel to the signal carrier conductors (see figure) in the wiring channel for the purpose of shielding the signal wires from cross-talk. Ground pads for this purpose are identified in the figure. The reduction in noise coupling accomplished by use of this technique will allow the use of faster rise-time output drivers on the chip, thereby contributing to improved module performance. Also, by its use, the buried EC approach can be further extended to the benefit of higher performance modules with driver rise-times in the vicinity of 250 picoseconds, to the betterment of overall machine performance. No tooling changes are involved in the use of this technique si...