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Improved Switching Circuit for Off-Chip Drivers

IP.com Disclosure Number: IPCOM000060380D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Reedy, DC: AUTHOR [+2]

Abstract

A circuit is described which provides simultaneous switching of multiple off-chip drivers. The circuit includes a push-pull output and a selectable high impedance input. The circuit, shown in the schematic diagram includes two inverters (T1, T3, R1, R2, R3, R5 and T2, T5, R4) which are interconnected by T4 for push-pull operation with resistor R1 common to both. With the input at a logic 0, T1 and T2 are on, T3 and T5 are off and T4 is on. This establishes a logic 1 at the output. The DC up-level is determined by R5 and R6 and the overshoot clamping network consisting of diodes D1, D2 and D3. When the input switches to a logic 1, the bases and collectors of T1 and T2 will begin to rise. Base current to T3 is provided by the path consisting of VCC, R2 and R3.

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Improved Switching Circuit for Off-Chip Drivers

A circuit is described which provides simultaneous switching of multiple off-chip drivers. The circuit includes a push-pull output and a selectable high impedance input. The circuit, shown in the schematic diagram includes two inverters (T1, T3, R1, R2, R3, R5 and T2, T5, R4) which are interconnected by T4 for push-pull operation with resistor R1 common to both. With the input at a logic 0, T1 and T2 are on, T3 and T5 are off and T4 is on. This establishes a logic 1 at the output. The DC up-level is determined by R5 and R6 and the overshoot clamping network consisting of diodes D1, D2 and D3. When the input switches to a logic 1, the bases and collectors of T1 and T2 will begin to rise. Base current to T3 is provided by the path consisting of VCC, R2 and R3. Base current to T5 will be provided by the path consisting of VCC, R1, the base-collector Schottky diode of T2, and R4. By proper selection of R2, R3 and R1, R4, T3 will turn on, resulting in T4 turning off prior to T5 turning on. This eliminates unwanted transient current in T4. The rate at which the base current of T5 increases is controlled, which limits di/dt in output transistor T5 to acceptable levels under full load. When the input switches to a logic 0, Tl and T2 turn on, resulting in T3 and T5 turning off. The di/dt rate of T4 is determined by the values of R5, R6 and the capacitance at the base of T4. The nominal average circuit delay for a capacitive ...