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Chip-Level Self-Testing Circuit for High Density Circuits

IP.com Disclosure Number: IPCOM000060389D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 4 page(s) / 38K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+2]

Abstract

The basic self-test structure is built onto each logic chip, as shown in Fig. 1. Normal system shift register latches (SRLs) (shown vertically down the center of the figure) are divided into groups of j+1 SRLs each, beginning at the scan-in port of the chip. The last group, which would normally terminate at the scan-out port of the chip, contains j+1 or fewer SRLs, depending upon the SRL count in the scan string. The SRL string shown in Fig. 1 contains (j+1) (r-1) + k+1 SRLs. The first SRL in each group is modified for testing and is called an A-type SRL. All other SRLs (the B types shown in Fig. 1) are unmodified. Additionally, a linear feedback shift register (LFSR) and a multiple input shift register (MISR) are built onto the chip. The LFSR and the MISR constructions are shown in Figs. 3 and 4, respectively.

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Chip-Level Self-Testing Circuit for High Density Circuits

The basic self-test structure is built onto each logic chip, as shown in Fig. 1. Normal system shift register latches (SRLs) (shown vertically down the center of the figure) are divided into groups of j+1 SRLs each, beginning at the scan-in port of the chip. The last group, which would normally terminate at the scan-out port of the chip, contains j+1 or fewer SRLs, depending upon the SRL count in the scan string. The SRL string shown in Fig. 1 contains (j+1) (r-1) + k+1 SRLs. The first SRL in each group is modified for testing and is called an A-type SRL. All other SRLs (the B types shown in Fig. 1) are unmodified. Additionally, a linear feedback shift register (LFSR) and a multiple input shift register (MISR) are built onto the chip. The LFSR and the MISR constructions are shown in Figs. 3 and 4, respectively. In those figures, the SRLs shown are scan-only SRLs with no system data ports and are clocked only by the normal A and B scan clocks. As shown in Fig. 1, the Scan Data input to the LFSR (Fig. 3) is wired on the logic chip to the scan-out of the last system SRL in the scan string of the chip, the Scan Data Out of the LFSR is wired to the Scan Data Input of the MISR (Fig. 4), and the Scan Data Out of the MISR is wired to the chip scan-out port. Thus, the system SRLs are connected into a single scan-path in series with the LFSR and the MISR. Additionally, a chip input pin is assigned to carry the +Test Mode signal onto the chip, with an on-chip inverter driven by the signal to provide its inverse (-Test Mode). Consider the LFSR and MISR circuits shown in Figs. 3 and
4. When the +Test Mode line is at a logical "0" or off, the feedback paths of both the LFSR and the MISR are disabled and the parallel inputs to the MISR are held at a logical "0". Thus, the serial data applied to the Scan Data inputs of both the LFSR and MISR will appear unaltered at the Scan Data Out after the requisite number of AB scan clock cycles. When in the test mode (with +Test Mode at a logical "1"), the LFSR feedback implements a primitive polynomial and the LFSR cycles autonomously through the states of a maximum length linear sequence in synchronization with the AB scan clocks. Also, when in test mode the MISR acts as a parallel input data compressor. Both functions (LFSR and MISR) are well known. The type A SRLs, shown in Fig. 1 as the first in each group of j+1 SRLs, are standard system SRLs with added circuitry on their scan data inputs, as shown in Fig. 2. When not in test mode (+Test Mode at a logical "0"), the type A SRLs function normally as system latches using one or more system data inputs and system clocks, or as scan elements using the scan data input and the scan A and B clocks. In test mode (+Test Mode at a logical "1") the outputs of individual stages of the LFSR are gated into the type A SRLs through the scan data input of the SRL in clock synchronization with the scan clocks, an...