Browse Prior Art Database

Indirect Program Access for a Signal Processor

IP.com Disclosure Number: IPCOM000060413D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Esteban, DJ: AUTHOR [+2]

Abstract

The signal processor state-of-the-art machines often use separate instruction and data memories. In such configurations the processor itself normally does not have the ability to write its own instruction memory. This memory has ordinarily read-only storage, but in some cases where random-access memory (RAM) is used, this memory may be IPLed (Initially Program Loaded) by separate DMA access controller devices with appropriate code for start-up. The present design processor implements an indirect program access feature in the arithmetic section of the processor which enables it to read and write the program RAM memory without the requirement of any additional external hardware. With this feature, programs to be loaded into instruction memory enter on the ordinary data bus, as would be done with conventional input data.

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Indirect Program Access for a Signal Processor

The signal processor state-of-the-art machines often use separate instruction and data memories. In such configurations the processor itself normally does not have the ability to write its own instruction memory. This memory has ordinarily read-only storage, but in some cases where random-access memory (RAM) is used, this memory may be IPLed (Initially Program Loaded) by separate DMA access controller devices with appropriate code for start-up. The present design processor implements an indirect program access feature in the arithmetic section of the processor which enables it to read and write the program RAM memory without the requirement of any additional external hardware. With this feature, programs to be loaded into instruction memory enter on the ordinary data bus, as would be done with conventional input data. By use of special branch instruction operations which control the flow of the pipelined architecture implemented in this processor, the instructions to be written are applied to the instruction memory using the address and access busses normally used for storing data in the memory. This has an additional advantage in that instructions to be loaded can be error checked prior to loading. Furthermore, this facility provides the capability of bringing instructions from the instruction memory into the arithmetic section of the processor without execution. In this manner, instructions may be diagnosed or transferred to another device or system through the common data bus as conventional data. Fig. 1 illustrates the overall flow diagram of the signal processor implementing this indirect program access feature. It is a three-phase pipeline processor structure having the operational sequence of fetch, address generate, and transfer/compute. Branch operations are designed to be completed after the second phase, i.e., address generation. This results in the busses associated with the data memory, the common data bus 4 and the common address bus 23 being vacant or unused on the third phase of the branch instruction execution. Both of these busses can therefore be used in parallel during phase three of the three-phase pipeline sequence to move a full instruction of 24 bits and 3 parity bits from some point external to the processor for writing in the instruction store in memory 24. Two special branch instructions are utilized. The branch indirect progra...