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Dual-Ported Bus Structure With Asynchronous DMA Handshake

IP.com Disclosure Number: IPCOM000060433D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Dwyer, H: AUTHOR

Abstract

This article describes a bus structure that provides high direct memory access (DMA) data rates, low overhead for the communicating units' processors and a flexible method of command/data transfer between the intelligent units without bus arbitration with its accompanying performance overhead and complexity. The structure is seen in Fig. 1. Units A, B, and C are all functional units containing microprocessor systems. A's do not communicate with other A's, but all A's communicate with B and B with all A's. B and C also communicate with each other. D has no microprocessor and is tightly bound to C with a special bus. The A to B interface is seen in Fig. 2. The "A" units contain both a Command Port and a DMA Port. They are memory mapped into both the address space of the A unit and the address space of the B unit.

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Dual-Ported Bus Structure With Asynchronous DMA Handshake

This article describes a bus structure that provides high direct memory access (DMA) data rates, low overhead for the communicating units' processors and a flexible method of command/data transfer between the intelligent units without bus arbitration with its accompanying performance overhead and complexity. The structure is seen in Fig. 1. Units A, B, and C are all functional units containing microprocessor systems. A's do not communicate with other A's, but all A's communicate with B and B with all A's. B and C also communicate with each other. D has no microprocessor and is tightly bound to C with a special bus. The A to B interface is seen in Fig. 2. The "A" units contain both a Command Port and a DMA Port. They are memory mapped into both the address space of the A unit and the address space of the B unit. This allows for flexible access by the microprocessors. The Command Port is designed so that simultaneous transfers can occur; i.e., it can be written into by both microprocessors at the same time or it can be read from by both microprocessors at the same time. COMMAND/DATA TRANSFERS THROUGH CMD PORT Whenever A or B wants to communicate with the other unit, it writes a command to the Command Port. This act causes an interrupt on the destination unit and also sets a memory-mapped flag in the source unit (Fig. 3). When the destination unit responds to the interrupt and reads the Command Port, both the interrupt and the Flag are reset. By monitoring the Flag, the source unit can determine if the Command Port has been read yet by the destination unit making it available for another transfer. The amount of data transmitted per interrupt can be doubled if no DMA process is in progress. The source unit then writes data to the DMA port (described later) first and then the Command Port. Upon receiving an interrupt, the destination unit reads the DMA port first and then the Command Port. All these ports are memory-mapped on both units. DMA TRANSFERS All DMA transfers take place through the DMA Port and can proceed concurrently with Command Port transfers. Each unit sets up the DMA transfer on its own DMA controller. The information for the transfer (who wants it, which direction, how many bytes, etc.) i...