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Signal Margin TEST for 4-D, 4-D With Poly Load or 6-D Random Access Memories

IP.com Disclosure Number: IPCOM000060437D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Dreibelbis, JH: AUTHOR [+2]

Abstract

Memory array margins may be determined during the test phase through the utilization of a capacitive voltage divider which is programmed by an external voltage source. The CMOS circuitry utilized for signal margin testing is shown in Fig. 1. During standby, Data line (DL) and Data Line "not" (DL "not") are precharged (PC) high to VDD by Bit Line PC "not" (BLPC "not") and the Clock (CLK) is low so that the voltage levels on PAD "X" and PAD "Y" are transferred into nodes A and B. Then, when CLK is high, nodes A and B are isolated from DL and DL "not". To test for signal margins, CLK "not" will go low and CLK will go high after BLPC "not" goes high and before the Data Line goes high. Depending on the levels in nodes A and B, DL and DL "not" will drop by a value WV < (VDD - V) C/(C + CDL "not").

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Signal Margin TEST for 4-D, 4-D With Poly Load or 6-D Random Access Memories

Memory array margins may be determined during the test phase through the utilization of a capacitive voltage divider which is programmed by an external voltage source. The CMOS circuitry utilized for signal margin testing is shown in Fig. 1. During standby, Data line (DL) and Data Line "not" (DL "not") are precharged (PC) high to VDD by Bit Line PC "not" (BLPC "not") and the Clock (CLK) is low so that the voltage levels on PAD "X" and PAD "Y" are transferred into nodes A and B. Then, when CLK is high, nodes A and B are isolated from DL and DL "not". To test for signal margins, CLK "not" will go low and CLK will go high after BLPC "not" goes high and before the Data Line goes high. Depending on the levels in nodes A and B, DL and DL "not" will drop by a value WV < (VDD - V) C/(C + CDL "not"). Note that VT is no longer in the equation; therefore, the signal margin test is more accurate. TEST PROCEDURE 1) To measure the signal, SHMOO PAD "X" and PAD "Y". a) Write all "ONE", then Read with PAD "Y" at VDD and PAD "X" "Schmooed". b) Write all "ZERO", then Read with PAD "X" at VDD and PAD "Y" "Schmooed". 2) To increase the signal, a) Write all "ONE", then Read with PAD "X" at VDD and PAD "Y" "Schmooed". b) Write all "ZERO", then Read with PAD "Y" at VDD and PAD "X" "Schmooed". 3) Normal Operation. a) Both PAD "X" and PAD "Y" at VDD. This margin test could be extended to the case when DL and DL...