Browse Prior Art Database

Adaptive Interrupt Sharing

IP.com Disclosure Number: IPCOM000060446D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Heath, CA: AUTHOR [+4]

Abstract

This article describes an extended form of interrupt sharing for personal computer (PC) peripherals, which allows for switching between different interrupt request signalling paths, one path providing conventional PC request handling and the other providing shared request handling under control of system supervisory software. The interrupt request (IRQ) circuits for most of the existing PC I/O adapters are implemented such that when the circuit is enabled, the IRQ signal to the PC I/O channel stays "low" during the non-active state. The IRQ line is set "high" when interrupt is requested. With this mechanism, only one device can be enabled for each interrupt level. The low state device overrides the high state device.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Adaptive Interrupt Sharing

This article describes an extended form of interrupt sharing for personal computer (PC) peripherals, which allows for switching between different interrupt request signalling paths, one path providing conventional PC request handling and the other providing shared request handling under control of system supervisory software. The interrupt request (IRQ) circuits for most of the existing PC I/O adapters are implemented such that when the circuit is enabled, the IRQ signal to the PC I/O channel stays "low" during the non-active state. The IRQ line is set "high" when interrupt is requested. With this mechanism, only one device can be enabled for each interrupt level. The low state device overrides the high state device. Therefore, unless all the enabled devices on the same IRQ level are issuing interrupt requests, the programmable interrupt controller never senses the interrupt request. These PC interrupt sharing schemes can handle interrupt sharing only under the following conditions: 1. All enabled interrupt devices sharing the same interrupt level must implement the same identical interrupt sharing hardware design. 2. Interrupt handler routine has to be written to handle the "daisy chain" handler structure. 3. An IO write (IOW) to H"02Fx" must be issued at the end of each interrupt handler routine before exit of the interrupt service routine (i.e., IOW at H"02F3" must be issued for device interrupt handlers that share the interrupt request level 3'IRQ3'). The technique disclosed herein supports batch operation of existing hardware design and also provides the interrupt sharing capability that can share interrupt for upward software compatibility. A "switching" scheme is prese...