Browse Prior Art Database

Emulator Synchronism

IP.com Disclosure Number: IPCOM000060453D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Gorga, KJ: AUTHOR [+3]

Abstract

To provide for data transfer at a maximum rate between a host system and a PC running a terminal emulator, alphanumeric replacement (ANR) hardware is allowed to share the PC direct-memory access (DMA) channels between the ANR card and the disk control cards. When this was done, a method to interlock the host computer and the ANR hardware was created so that no data was lost during an upload or download operation. The ANR interface in the host computer had a provision for a busy signal, but it was only recognized at idle poll time or during the first read poll of a read/write sequence to the ANR card. To interlock the PC microprogram to the host computer, a Busy Pending Latch was added to the ANR card. This gives the PC complete control of setting the busy signal to the host controller.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Emulator Synchronism

To provide for data transfer at a maximum rate between a host system and a PC running a terminal emulator, alphanumeric replacement (ANR) hardware is allowed to share the PC direct-memory access (DMA) channels between the ANR card and the disk control cards. When this was done, a method to interlock the host computer and the ANR hardware was created so that no data was lost during an upload or download operation. The ANR interface in the host computer had a provision for a busy signal, but it was only recognized at idle poll time or during the first read poll of a read/write sequence to the ANR card. To interlock the PC microprogram to the host computer, a Busy Pending Latch was added to the ANR card. This gives the PC complete control of setting the busy signal to the host controller. As seen in the schematic, the Busy bit from the command latch FF2 is sent to the host controller in response to a Poll command. Writing the Command Latch will immediately latch the Busy bit in FF2 and allow it to be reported to the host controller on a subsequent Poll command. Writing a 1 to FF1 will set the Busy Pending Latch. The status of the latch can be read through tristate buffer TS1. A Read Poll command will have the Rd Cmd Bit on resulting in a 0 level from NOR 1 and a 1 level from NAND 1. This is a no-action state. A Poll command will have a 0 level on Rd Cmd Bit, 0 on Poll Cmd Bit, and a 0 level on Busy Pending Rd, resulting in a 1 output from NOR 1....