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Overlapped Processing During SVC Instructions

IP.com Disclosure Number: IPCOM000060456D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

McDermott, MJ: AUTHOR [+2]

Abstract

On many multi-processor systems, when a Supervisor Call (SVC) instruction is issued, no other code is executed until the SVC is processed. Often, other tasks are ready to execute, yet for the duration of the SVC the main processor is not active. The duration of the average SVC may be several hundred microseconds. Overlapped SVC processing reduces the main processor idle time by providing increased processing overlap. Figs. 1 and 2 compare the task switching and SVC processing of a uniprocessor system and a multiprocessor system using the invention. On a uniprocessor system, when a supervisor call is issued, the processor stops executing application code, processes the supervisor call, then returns to the application code (Fig. 1).

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Overlapped Processing During SVC Instructions

On many multi-processor systems, when a Supervisor Call (SVC) instruction is issued, no other code is executed until the SVC is processed. Often, other tasks are ready to execute, yet for the duration of the SVC the main processor is not active. The duration of the average SVC may be several hundred microseconds. Overlapped SVC processing reduces the main processor idle time by providing increased processing overlap. Figs. 1 and 2 compare the task switching and SVC processing of a uniprocessor system and a multiprocessor system using the invention. On a uniprocessor system, when a supervisor call is issued, the processor stops executing application code, processes the supervisor call, then returns to the application code (Fig. 1). On the IBM System/36, when an SVC is issued, the Control Store Processor (which normally handles low-level operating- system tasks) (CSP) restarts the Main Store Processor (which normally executes application programs) (MSP) with a different task. Then the CSP processes the SVC on a lower priority interrupt level at the same time that the MSP executes code for the other task. The MSP is switched from executing code for one task to the next with minimal idle time.

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The dispatcher function of the supervisor keeps a 'next ready task' available while the MSP is executing instructions from a different task. This 'next ready task' is the highest priority task that is ready to execut...