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Two CLOCK Frequencies Controlled Sequencer for a Processor

IP.com Disclosure Number: IPCOM000060459D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Desrosiers, B: AUTHOR [+4]

Abstract

In a processor chip which has to sequentially perform a bus operation (load), internal function execution and bus operation (store), a sequencer is provided to deliver the various machine state information in synchronism with interface bus clocks or with internal clocks or with a mix of both. By using two independent time references, the internal function execution is performed with the best performance by choosing the appropriate internal clock frequencies. Processors built according to the Level Sensitive Scan Design (LSSD) technique are integrated in a chip which is a double latch, synchronous design and time controlled by 2 sets of clocks: Interface Bus clocks for input/output (I/O) operations and Internal clocks for the internal function execution.

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Two CLOCK Frequencies Controlled Sequencer for a Processor

In a processor chip which has to sequentially perform a bus operation (load), internal function execution and bus operation (store), a sequencer is provided to deliver the various machine state information in synchronism with interface bus clocks or with internal clocks or with a mix of both. By using two independent time references, the internal function execution is performed with the best performance by choosing the appropriate internal clock frequencies. Processors built according to the Level Sensitive Scan Design (LSSD) technique are integrated in a chip which is a double latch, synchronous design and time controlled by 2 sets of clocks: Interface Bus clocks for input/output (I/O) operations and Internal clocks for the internal function execution. For a given operation, the appropriate clock pulses have to be selected to start and end the various machine states at the correct times and, in some cases, as early as possible to maintain a good performance. Selected clock pulses are distributed by the clock distribution logic; they feed the Sequencer (cycle counter) which delivers the current machine state. These selected clock pulses are also distributed to registers to control the time when the registers are loaded and unloaded. These bus clocks are used by the processor to communicate with the external world. The BUS RECEIVE CLOCK (Master latches clock R) is used to load the processor registers with data from the Interface Data Bus. The BUS SEND CLOCK (Slave latches clock S) is used to synchronize the data sent by the processor on the Data bus. The INTERNAL C-CLOCK and INTERNAL B- CLOCK are used to load/unload the processor registers during internal execution. The basic clock increment is given by the Internal clock period. The Bus clock period can be any integer number multiple of the basic clock increment provided that a BUS S-CLOCK pulse or a BUS R-CLOCK pulse always occurs in phase with an INTERNAL B-CLOCK pulse or an INTERNAL...