Browse Prior Art Database

Memory Data Hold Register

IP.com Disclosure Number: IPCOM000060463D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Pearce, RW: AUTHOR [+4]

Abstract

The figure illustrates the use of a memory interface which permits the coupling of a slow core memory circuit or a fast integrated memory circuit to a plurality of processors. A processor 10 includes, at least, an instruction register 12, a data register 14, a microcode register 16 and a program counter 18. In executing an instruction, the processor 10 generates and transmits a bus request to a memory system 20. Outputs of the program counter 18 are coupled to a memory address expansion RAM (random-access memory) 22 and a memory address register 24. The program counter 18 and the memory address expansion RAM 22 facilitate the generation of an expanded address which is stored in the memory address register 24. The expanded address enables the addressing of a larger number of memory cells in the memory system 20.

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Memory Data Hold Register

The figure illustrates the use of a memory interface which permits the coupling of a slow core memory circuit or a fast integrated memory circuit to a plurality of processors. A processor 10 includes, at least, an instruction register 12, a data register 14, a microcode register 16 and a program counter 18. In executing an instruction, the processor 10 generates and transmits a bus request to a memory system 20. Outputs of the program counter 18 are coupled to a memory address expansion RAM (random-access memory) 22 and a memory address register 24. The program counter 18 and the memory address expansion RAM 22 facilitate the generation of an expanded address which is stored in the memory address register 24. The expanded address enables the addressing of a larger number of memory cells in the memory system 20. In a microcoded processor, such as processor 10, a memory operation is started at the beginning of one microcycle and memory data is loaded into registers, such as the instruction register 12 or the data register 14, at the beginning of a subsequent microcycle. In executing a register-to-register floating-point instruction, which may be 40 microinstructions in length, the memory operation to fetch the next instruction can be started immediately. However, memory data does not have to be loaded into the instruction register 12 or the data register 14 until the execution of the floating- point instruction is complete. In order to pre...