Browse Prior Art Database

Lagging Address Register Mechanism

IP.com Disclosure Number: IPCOM000060465D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Laurent, B: AUTHOR [+3]

Abstract

The Lagging Address Register (LAR) is a "came from" register. When displayed by the operator or by the program, the LAR contains the address of the last instruction executed prior to the instruction that is currently being executed, if any. The LAR mechanism is intended to help the programmer in knowing the address of the last instruction executed prior to the occurrence of specific events, such as programming errors, data protection errors, adapter communication errors, etc. The control program can load the contents of LAR into a general register by executing an input instruction. The control program can then either examine the contents of the general register or display the address on the control panel by using the general register as input to the display registers. The LAR register updating mechanism is shown in Fig. 1.

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Lagging Address Register Mechanism

The Lagging Address Register (LAR) is a "came from" register. When displayed by the operator or by the program, the LAR contains the address of the last instruction executed prior to the instruction that is currently being executed, if any. The LAR mechanism is intended to help the programmer in knowing the address of the last instruction executed prior to the occurrence of specific events, such as programming errors, data protection errors, adapter communication errors, etc. The control program can load the contents of LAR into a general register by executing an input instruction. The control program can then either examine the contents of the general register or display the address on the control panel by using the general register as input to the display registers. The LAR register updating mechanism is shown in Fig. 1. During a normal instruction Fetch, the LAR is updated if the Command Register, which records the type of operation to the Storage, contains a Start Main Storage Read Instruction (SMSRI). This updating occurs at Close Main Storage Read Instruction (CLMSRI) time which is scheduled 3 cycles after SMSRI, and is performed by transferring the instruction address register (IAR) in the LAR at that time. The IAR content is the current instruction address plus 2, except when a branch instruction is executed. During a branch instruction fetch (SMSRB), the LAR is not updated. Fig. 2 shows the LAR timing diagram during the normal instruction Fetch. If the instruction executed at 202 is a Read LAR, then B Reg ==> 200. If the instruction executed at 204 is a Read LAR, then B Reg ==> 202. If the instruction executed at 400 is a Read LAR, then B Reg ==> 206. Instruction 206 is a branch instruction. In a communication controller, there are eight inhibit conditions which prevent LAR updating, namely: 1 - Invalid operation code 2 - I/O operation attempt in program level 5 3 - Storage protect or address exception in instruction Fetch 4 - Storage protect or address exception in Load or Store 5 - Adapter interface check during a program initiated operation (PIO) 6 - Adapter interface check during an adapter initiated operation (AIO) 7 - Address compare in instruction fetch 8 - Address compare in Load or Store When those conditions occur, the LAR value read must be the address of the last instruction executed before the one that caused the check. Figs. 3 to 9 show the LAR timing diagrams when conditions 1 or 2 and conditions 3 to 9, respectively, occur. In Fig. 3, X means the detection of either an Invalid Operation or an I/O operation in Level 5. At this point the machine changes the current environment, so as to point to the address corresponding to the error processing (in the above example it is set to 400). Therefore, if the instruction executed at 400 is a Read LAR, the value delivered by the machine in the B register will be 202, corresponding to the address of the last instruction executed bef...