Browse Prior Art Database

Trigger Circuit With Hysteresis

IP.com Disclosure Number: IPCOM000060471D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

A trigger circuit is described which improves the performance of high density complementary metal-oxide-silicon (CMOS) dynamic random-access memories (DRAMs). During a memory cell access, the trigger circuit senses the word line transition and provides a delay to permit full signal transfer before initiating the bit line sensing operation. The circuit incorporates a high degree of hysteresis in its transfer characteristic, having a high unity gain point for rising inputs and a low unity gain point for falling inputs. The trigger circuit, as shown in Fig. 1, is implemented using a CMOS NAND gate along with a CMOS inverter and transistors TP1, TP2, TN1, and TN2.

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Trigger Circuit With Hysteresis

A trigger circuit is described which improves the performance of high density complementary metal-oxide-silicon (CMOS) dynamic random-access memories (DRAMs). During a memory cell access, the trigger circuit senses the word line transition and provides a delay to permit full signal transfer before initiating the bit line sensing operation. The circuit incorporates a high degree of hysteresis in its transfer characteristic, having a high unity gain point for rising inputs and a low unity gain point for falling inputs. The trigger circuit, as shown in Fig. 1, is implemented using a CMOS NAND gate along with a CMOS inverter and transistors TP1, TP2, TN1, and TN2. The NAND circuit, comprised of transistors TP3, TP4, TN3, and TN4, holds the output node OUT at ground until the voltage on one of the dummy word lines (DWL1, DWL2) falls. When the voltage on DWL1 or DW2 falls, the trigger circuit delays the rising edge of the signal at OUT. The function of the trigger circuit may be applied to any CMOS input gate (NAND, NOR, INVERTER). The CMOS inverter is comprised of transistors TP5 and TN5 and provides an inversion of signals at OUT for negative feedback (FDBK) to transistors TP2 and TN2. Without this trigger circuit, the transfer characteristic of the NAND would be similar to case 2 in FIG. 2, tracing the same path for both rising and falling inputs. Adding transistors TP1 and TN1 in series between the NAND circuit and Vdd and ground, re...