Browse Prior Art Database

Microprocessor With a Selectable PLA Bypass

IP.com Disclosure Number: IPCOM000060474D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Pearce, RW: AUTHOR [+2]

Abstract

A microprocessor is designed to efficiently execute a first instruction set using a PLA for microcode vectoring and, in another application, execute a second instruction set using a PLA bypass feature. Referring to Fig. 1, a primary input of the microprocessor 10 is coupled to a reference potential which enables a multiplexer 12 to selectively couple the PLA 14 or an instruction register 16 to a microaddress generator 18. The PLA 14 decodes instruction op codes for the first instruction set and points to starting addresses for the execution thereof in microcode. If an instruction from the second instruction set is to be executed, the PLA 14 is bypassed by the multiplexer 12, as noted above. Thereafter, an eight-bit op code of instruction stored in the instruction register 16 is routed into the microaddress generator 18.

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Microprocessor With a Selectable PLA Bypass

A microprocessor is designed to efficiently execute a first instruction set using a PLA for microcode vectoring and, in another application, execute a second instruction set using a PLA bypass feature. Referring to Fig. 1, a primary input of the microprocessor 10 is coupled to a reference potential which enables a multiplexer 12 to selectively couple the PLA 14 or an instruction register 16 to a microaddress generator 18. The PLA 14 decodes instruction op codes for the first instruction set and points to starting addresses for the execution thereof in microcode. If an instruction from the second instruction set is to be executed, the PLA 14 is bypassed by the multiplexer 12, as noted above. Thereafter, an eight- bit op code of instruction stored in the instruction register 16 is routed into the microaddress generator 18. The op code is stored in the microaddress generator 18 so that it occupies bit positions 3 through 10, as shown in Fig. 2. Moreover, as is shown in Fig. 2, the op code is shifted one bit position in the microaddress generator 18 to allow two locations in a microcode PROM 20 for the execution of instruction. If the execution of instruction requires more than two locations, a jump must be performed to a blank section of the microcode PROM 20. A "1" is stored in bit position 2 in order to address a spare section of the microcode PROM 20. As shown in Fig. 2, the microaddress generator 18 generates an addres...