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Memory Data Available Anticipation Circuit

IP.com Disclosure Number: IPCOM000060485D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Pearce, RW: AUTHOR [+4]

Abstract

A microprocessor is designed to reactivate its internal clocks subsequent to a request for memory access but prior to the receipt of memory data. Referring to Fig. 1, a microprocessor 10 includes, at least, an instruction register 12, a data register 14, a microcode register 16, a microaddress generator 18, a microcode PROM (programmable read-only memory) 20 and a program counter 22. In executing an instruction, the processor 10 generates and transmits a bus request to a memory system 24. Outputs of the program counter 22 are coupled to a memory address expansion RAM (random-access memory) 26 and a memory address register 28. The program counter 22 and the memory address expansion 26 facilitate the generation of an expanded address which is stored in the memory address register 28.

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Memory Data Available Anticipation Circuit

A microprocessor is designed to reactivate its internal clocks subsequent to a request for memory access but prior to the receipt of memory data. Referring to Fig. 1, a microprocessor 10 includes, at least, an instruction register 12, a data register 14, a microcode register 16, a microaddress generator 18, a microcode PROM (programmable read-only memory) 20 and a program counter 22. In executing an instruction, the processor 10 generates and transmits a bus request to a memory system 24. Outputs of the program counter 22 are coupled to a memory address expansion RAM (random-access memory) 26 and a memory address register 28. The program counter 22 and the memory address expansion 26 facilitate the generation of an expanded address which is stored in the memory address register 28. The expanded address enables the addressing of a larger number of memory cells in the memory system 24. In microprocessor 10, a memory operation is started at the beginning of one cycle and memory data is loaded into registers, such as the instruction register 12 or the data register 14, at the beginning of a subsequent cycle. In executing a register-to-register floating- point instruction, which may be 40 microinstructions in length, the memory operation to fetch the next instruction can be started immediately. However, memory data does not have to be loaded into the instruction register 12 or the data register 14 until the execution of the floating-point instruction is complete. In order to prefetch subsequent instructions and/or data and also enable the memory system 24 to serve other processors while the microprocessor 10 completes the execution of the floating-point instruction, the memory data is loaded into a memory data hold register (MDHR) 30. S...