Browse Prior Art Database

Separate Microcode-Controlled WRITE Lines for DATA and ECC CHECK Bits

IP.com Disclosure Number: IPCOM000060487D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Burmeister, WF: AUTHOR [+5]

Abstract

By the use of separate microcode-controlled write lines for data and error correction code (ECC) check bits, errors can be forced into the data or check bit portions of a main storage array in order to completely test ECC logic or isolate failing memory chips. Any number of bits can be easily altered to improve diagnostic capabilities. As an example, single, double, or triple bit errors can be forced via microcode. A minimal amount of hardware, two latches, and one buffer/driver accomplish the error force. Referring to the figure, assume an error is to be forced into the data at location "A"of the Data Array. Good data is used to generate the check bits in the ECC logic. The CHECK BIT WRITE ENABLE latch 1 is set, and the check bits are written into location "A" of the Check Array.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Separate Microcode-Controlled WRITE Lines for DATA and ECC CHECK Bits

By the use of separate microcode-controlled write lines for data and error correction code (ECC) check bits, errors can be forced into the data or check bit portions of a main storage array in order to completely test ECC logic or isolate failing memory chips. Any number of bits can be easily altered to improve diagnostic capabilities. As an example, single, double, or triple bit errors can be forced via microcode. A minimal amount of hardware, two latches, and one buffer/driver accomplish the error force. Referring to the figure, assume an error is to be forced into the data at location "A"of the Data Array. Good data is used to generate the check bits in the ECC logic. The CHECK BIT WRITE ENABLE latch 1 is set, and the check bits are written into location "A" of the Check Array. The DATA WRITE ENABLE latch 2 is set while the CHECK BIT WRITE ENABLE latch is reset. Via microcode, a bit error is then "forced" into the data of the Data Array originally used to generate the check bits. This "bad" data is then written into location "A". Upon reading both data and the check bits from memory, the ECC logic will correct the error. In addition to testing ECC logic, a failing array chip can be detected and isolated using the separate write lines and the appropriate data and check bit patterns.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]