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Expansion of Limited Microprocessor Address Space Via an Address Windowing Mechanism

IP.com Disclosure Number: IPCOM000060495D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Buonomo, JP: AUTHOR [+6]

Abstract

Microprocessor (mP)-based computing systems are designed with a limit on the amount of memory that can be accessed. This architected 'address space' is primarily a function of the internal addressing structure of the mP and is used to access general-purpose random-access memory (RAM). In a complete system design, additional requirements may be placed on the address space to support resident Operating Systems in read-only memory (ROM), or additional peripheral devices, such as displays, disk drives, or printers, that require large memory buffer areas. When the access to these additional memory areas is made through the memory address space, as defined by the 'system' architecture, the amount of RAM that can be accessed by the mP is constrained further.

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Expansion of Limited Microprocessor Address Space Via an Address Windowing Mechanism

Microprocessor (mP)-based computing systems are designed with a limit on the amount of memory that can be accessed. This architected 'address space' is primarily a function of the internal addressing structure of the mP and is used to access general-purpose random-access memory (RAM). In a complete system design, additional requirements may be placed on the address space to support resident Operating Systems in read-only memory (ROM), or additional peripheral devices, such as displays, disk drives, or printers, that require large memory buffer areas. When the access to these additional memory areas is made through the memory address space, as defined by the 'system' architecture, the amount of RAM that can be accessed by the mP is constrained further. This problem is encountered when large data-intensive application programs are written for mP-based systems or in the design of loosely coupled mP based multiprocessing systems where each mP requires full, direct access to the RAM of the other mP(s) in the system. An Address Windowing Mechanism can be used in a mP-based system to expand its memory address space indefinitely. This allows efficient access to large auxiliary RAM arrays through multiple dynamic windows addressed within the constraints of the address space of the source mP. This concept requires that a mapping address space 1 (Fig. 1) be set aside in the source mP 2 through which the dynamic windowing or 'mapping' operation occurs. This address space 1 becomes the gateway to access the significantly larger auxiliary RAM address space 3. Accesses from the mP 1 to the auxiliary RAM 3 can occur through any of the windows 4 in the address space 1. The contents of each of the windows 4 can be altered such that any location in the larger array can be accessed with no ordering or uniqueness requirements. The mapping hardware required consists of a small mapping array to perform the address conversion and miscellaneous control logic to load, enable, and disable the mapping hardware. The size requirements for the mapping array are dependent on the mapping address space, window, and auxiliary RAM size. In order to precisely define the array size, the following conventions are defined: Z = total mP address space in bytes Y = mapping addre...