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Method to Achieve CMOS ROX Isolation Using Lift-Off for Self-Aligning Implanted Areas

IP.com Disclosure Number: IPCOM000060514D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Dally, AJ: AUTHOR [+3]

Abstract

In the manufacture of semiconductors, there are various approaches to achieving ROX (recessed oxide) isolation in the CMOS (complementary metal oxide semiconductor). An invention proposes a method to achieve isolation which would eliminate one of the three masks required in the process. When using ROX for CMOS there is the need to offset the N well from the ROX edge. This is to avoid shorting the N well to the p-epi, and to avoid "sidewalk" beneath the poly-Si gate. The problem is illustrated in Fig. 1. The basic structure is shown in Fig. 1A, Si3N4 layer at 1, SiO2 at 2 and field implant doping at 3. In Fig. 1B, the N well implant 4 is not particularly high (about 1012 atoms/cc) and cannot compensate for the encroachment of P+ .

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Method to Achieve CMOS ROX Isolation Using Lift-Off for Self-Aligning Implanted Areas

In the manufacture of semiconductors, there are various approaches to achieving ROX (recessed oxide) isolation in the CMOS (complementary metal oxide semiconductor). An invention proposes a method to achieve isolation which would eliminate one of the three masks required in the process. When using ROX for CMOS there is the need to offset the N well from the ROX edge. This is to avoid shorting the N well to the p-epi, and to avoid "sidewalk" beneath the poly-Si gate. The problem is illustrated in Fig. 1. The basic structure is shown in Fig. 1A, Si3N4 layer at 1, SiO2 at 2 and field implant doping at 3. In Fig. 1B, the N well implant 4 is not particularly high (about 1012 atoms/cc) and cannot compensate for the encroachment of P+ . If the ROX is etched back, metallurgy will short the N well 5 to the substrate and leaking can occur in the border area under the poly-Si gate. A conventional CMOS isolation scheme is seen in the remaining sections of Fig. 1. If N well is done before ROX, as in Fig. 1C, then an extra mask 6 is required to offset 8 the N well 5 from the P+ field region, as in Fig. 1D. The N well mask is indicated at 7. The ROX mask 9 is applied in Fig. 1E, with a tighter P implant 10. This does not adversely affect the N well edge and serves to keep the field threshold up. The completion of the isolation process in Fig. 1F shows the N well being below the ROX 9 edge. The invention eliminates the need for an extra mask by using a reversal of the N well mask (by lifting off Al) to, in effect, fill-in and protect the N regio...