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Hardware Implementation of a Fast Transitional Recorder for Logic and Timing Analysis

IP.com Disclosure Number: IPCOM000060516D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Amirfaiz, F: AUTHOR

Abstract

A transitional recorder logic circuit is disclosed which replaces traditional random memory addressing and decoding with a sequential shift register memory having both timing and sense information. The timing and sense information in the register is comparatively updated at high speeds during a test sequence. The logic circuit eliminates the need for address registers and address decode logic while maximizing the use of available memory by having a common storage for trigger words and sense information. The figure shows a schematic block diagram of the transitional recorder logic circuit 10. The circuit is comprised of a shift memory register 11 having inputs from a latch logic module 12, clock counter 13 and AND gate 15 and output to a comparator 14.

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Hardware Implementation of a Fast Transitional Recorder for Logic and Timing Analysis

A transitional recorder logic circuit is disclosed which replaces traditional random memory addressing and decoding with a sequential shift register memory having both timing and sense information. The timing and sense information in the register is comparatively updated at high speeds during a test sequence. The logic circuit eliminates the need for address registers and address decode logic while maximizing the use of available memory by having a common storage for trigger words and sense information. The figure shows a schematic block diagram of the transitional recorder logic circuit 10. The circuit is comprised of a shift memory register 11 having inputs from a latch logic module 12, clock counter 13 and AND gate 15 and output to a comparator 14. In operation, the circuit 10 initially receives a probe input, having logic test sample data at data input bus 16 and a sample clock line 17. Data input bus 16 is received by latch module 12 while sample clock line 17 is being utilized by clock counter 13 and AND gate 15. Register 11 may have a trigger word initially stored in register position 21. Latch 12 will hold a current sample of data from bus 16 on every rising-edge of a clock signal pulse being sent on sample clock line 17. Count information is sent to register 11 by way of count bus 19 while current sample data is sent both to register 11 and comparator 14 by way of bus 18. Count information will be stored in reg...