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Hardware Interrupt Vectoring Circuit for Non-Compatible Peripherals

IP.com Disclosure Number: IPCOM000060518D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Tate, J: AUTHOR [+4]

Abstract

A technique is described whereby a circuit provides software programmable hardware vectoring of peripheral interrupts. The circuit is particularly useful to interface with processors which utilize multiple interrupt acknowledge cycles in the performance of interrupt vectoring. The circuit allows direct vectoring into interrupt service routines for peripherals which are not normally directly compatible with a processor's interrupt acknowledge circuitry. There are many peripheral devices which have the capability of placing a vector address or a portion of an address on their data bus, such as a communication controller. However, there are various families of peripherals which use different interrupt acknowledge sequences that prevent direct connection to a processor.

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Hardware Interrupt Vectoring Circuit for Non-Compatible Peripherals

A technique is described whereby a circuit provides software programmable hardware vectoring of peripheral interrupts. The circuit is particularly useful to interface with processors which utilize multiple interrupt acknowledge cycles in the performance of interrupt vectoring. The circuit allows direct vectoring into interrupt service routines for peripherals which are not normally directly compatible with a processor's interrupt acknowledge circuitry. There are many peripheral devices which have the capability of placing a vector address or a portion of an address on their data bus, such as a communication controller. However, there are various families of peripherals which use different interrupt acknowledge sequences that prevent direct connection to a processor. For example, one processor may require three Interrupt Acknowledge (INTA) cycles expecting an operational code (Opcode) to occur during the first cycle, while the low and high portions of the address occur during the second and third cycles. Another processor may require a byte vector from peripherals requiring only one INTA. The technique described herein provides a circuit to issue to a peripheral only the INTA needed to retrieve the byte vector while simultaneously assuring that the processor will receive all the data required during the other two cycles. The circuit consists of a three-state sequential circuit and two tri-state re...