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Timing-Influenced Layout Design

IP.com Disclosure Number: IPCOM000060522D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 6 page(s) / 53K

Publishing Venue

IBM

Related People

Burstein, M: AUTHOR [+2]

Abstract

This article describes a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring process. The approach is an extension of the hierarchical layout method, where placement and wiring are performed simultaneously [1]. A third phase of timing is added to the hierarchy, without affecting the computational complexity of the basic algorithm. Prior to the physical design, timing analysis is performed using statistical estimates for the unknown parameters, namely, the lengths of interconnecting wires. The output of this analysis includes a measure for each net that indicates the timing problem. These measures are used to bias the placement at the highest level of the hierarchy.

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Timing-Influenced Layout Design

This article describes a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring process. The approach is an extension of the hierarchical layout method, where placement and wiring are performed simultaneously [1]. A third phase of timing is added to the hierarchy, without affecting the computational complexity of the basic algorithm. Prior to the physical design, timing analysis is performed using statistical estimates for the unknown parameters, namely, the lengths of interconnecting wires. The output of this analysis includes a measure for each net that indicates the timing problem. These measures are used to bias the placement at the highest level of the hierarchy. Since wiring is performed after the partitioning process, the lengths of interconnecting nets among the partitions become available. These data are used to update the timing information that biases the design. Results show that, while delays due to interconnections are reduced, wireability of the chip does not deteriorate. Traditionally, the automatic physical design process for VLSI chips consists of a sequence of steps that are treated independently. The layout process is commonly performed in two steps, placement and wiring, to be followed by timing verification, for determining if the design is acceptable. If nets with intolerable delays are encountered, they are designated as critical and the process is repeated until an acceptable design is generated. The complexities of each of the steps are known to dictate such an approach. There are several problems with the above method, particularly for very large chips. 1. Treating placement, wiring and timing issues independently creates a cycle by which the analysis is performed a number of times before an acceptable layout is achieved. The reason for the cycle phenomenon is that a placed chip may not be wireable, and if it is, the resultant design may create critical nets with long delays. The current solution of ultimately replacing circuits, on the critical path, with ones that have less internal delays may not be sufficient to solve the problem. 2.The placement task is performed while ignoring interconnecting net delays. Shortening the interconnection among clocked elements, required to transmit a signal in a constraint period, was considered unimportant as the contribution to intra-chip wire delays was regarded insignificant. As the chip becomes larger in size and number of components, the average length of interconnection grows, consequently signal delays induced along long wires become critical. On the other hand, performing the placement process simultaneously with timing analysis remains to be computationally impractical. A recent study [2] which uses critical path weighting to derive the layout showed an improvement in circuit performance with respect to delays. We give an alternative efficient solu...