Browse Prior Art Database

Cover/Heat Sink Capacitor

IP.com Disclosure Number: IPCOM000060526D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Stadler, EE: AUTHOR [+2]

Abstract

To position a semiconductor chip decoupling capacitor as closely as possible to the chip, the latter is directly soldered to the cover of a module or a heat sink. The cover or the heat sink is designed as a high-frequency capacitor. The substrate voltage is applied across the rear side of the chip. Fig. 1 shows a first embodiment, wherein cover 1 takes the form of a capacitor. Chip 2 has its rear side connected to the capacitor, for instance, by soldering or by using a conductive epoxy resin, so that substrate voltage 3 is practically applied without any inductance. The other voltage 4, 5 is fed through chip carrier 6 along a low-inductance path. Seal 8 protects chip 2. The capacitor may also be designed for several potentials. Fig. 2 is a plan view of the connectors. Fig.

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Cover/Heat Sink Capacitor

To position a semiconductor chip decoupling capacitor as closely as possible to the chip, the latter is directly soldered to the cover of a module or a heat sink. The cover or the heat sink is designed as a high-frequency capacitor. The substrate voltage is applied across the rear side of the chip. Fig. 1 shows a first embodiment, wherein cover 1 takes the form of a capacitor. Chip 2 has its rear side connected to the capacitor, for instance, by soldering or by using a conductive epoxy resin, so that substrate voltage 3 is practically applied without any inductance. The other voltage 4, 5 is fed through chip carrier 6 along a low- inductance path. Seal 8 protects chip 2. The capacitor may also be designed for several potentials. Fig. 2 is a plan view of the connectors. Fig. 3 shows a second embodiment, wherein ceramic heat sink 7 takes the form of a decoupling capacitor. The remaining reference numerals designate the same voltages as in Fig. 1.

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