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Semiconductor Enhancement for High Speed Logic

IP.com Disclosure Number: IPCOM000060535D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+3]

Abstract

Disclosed is a process which improves semiconductor cost performance through separate extrinsic and intrinsic bases defined by submicron, self-aligned studs. The process begins after the semiconductor device has undergone a number of conventional processing steps through recessed oxide isolation (ROI). The basic structure is shown in Fig. 1. A nitride layer, which had been on the oxide layer 1, was stripped, and a fresh chemical vapor deposition (CVD) nitride layer 2 deposited on the oxide. A layer of photoresist (PR) 3 is next deposited, patterned with a mask and hardened. This is followed with the deposition of plasma oxide (SiOx) which is reactive ion etched (RIE) back to form vertical studs 4. Referring to Fig. 2, a block-out mask 5 is used to open the NPN base window.

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Semiconductor Enhancement for High Speed Logic

Disclosed is a process which improves semiconductor cost performance through separate extrinsic and intrinsic bases defined by submicron, self-aligned studs. The process begins after the semiconductor device has undergone a number of conventional processing steps through recessed oxide isolation (ROI). The basic structure is shown in Fig. 1. A nitride layer, which had been on the oxide layer 1, was stripped, and a fresh chemical vapor deposition (CVD) nitride layer 2 deposited on the oxide. A layer of photoresist (PR) 3 is next deposited, patterned with a mask and hardened. This is followed with the deposition of plasma oxide (SiOx) which is reactive ion etched (RIE) back to form vertical studs 4. Referring to Fig. 2, a block-out mask 5 is used to open the NPN base window. Boron 6 for the extrinsic base of the NPN is implanted through the nitride/oxide layers 2,1. Block-out mask 5 and photoresist 3 are stripped to obtain free-standing studs 4 (Fig. 3). A block-out mask 7, shown in Fig. 4, is used to remove unwanted studs 4a. The device is planarized with photoresist 8 as in Fig. 5. The resist is hardened and then RIE is used to expose the remaining studs 4. As illustrated in Fig. 6, the exposed studs are etched to form submicron openings 9 in the hardened resist 8 which is used as a mask to RIE down to the silicon surface 10. The resist is stripped, the device precleaned and a thin screen oxide 11 (Fig. 7) is grown o...