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Quick Early Castout From Store-In Caches

IP.com Disclosure Number: IPCOM000060542D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Most modern random-access memory systems incorporate error correction codes (ECC) that allow the correction of single bit errors. For a review and references see [1]. An exception to this rule is the high speed cache, where, for reasons of both time and space, simpler error detection schemes (e.g., parity) are commonly used. In the case of a store through cache, no increased vulnerability to memory errors is incurred by having only error detection (not error correction) in the cache memory, since main memory always has a valid copy of the data. In the case of a store-in cache, changed data in the cache comprise the only valid copy of the data in the system and are therefore subject to unrecoverable errors.

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Quick Early Castout From Store-In Caches

Most modern random-access memory systems incorporate error correction codes (ECC) that allow the correction of single bit errors. For a review and references see [1]. An exception to this rule is the high speed cache, where, for reasons of both time and space, simpler error detection schemes (e.g., parity) are commonly used. In the case of a store through cache, no increased vulnerability to memory errors is incurred by having only error detection (not error correction) in the cache memory, since main memory always has a valid copy of the data. In the case of a store-in cache, changed data in the cache comprise the only valid copy of the data in the system and are therefore subject to unrecoverable errors. Since the typical residency time of data in the cache is much shorter than the residency time in main memory, the risk is smaller and the cost/speed advantage of having only a simple error detection scheme for the cache memory outweighs the disadvantage of an occasional memory failure. A scheme is set forth that will allow a cache with memory traffic characteristics similar to a "store-in" cache and only single bit error detection (e.g., parity) to be much less susceptible to errors. If the usual "store-in" cache replacement strategy is modified to cause write back of changed lines on change of most recently used (MRU) status as suggested in [2], then the cache will contain changed data only in the MRU line of a congruence class. The MRU line in a congruence class is identified by bits in the cache directory, so, in this type of cache, the bits that record the changed status of...