Browse Prior Art Database

One Ghz Edge Triggered Multiplexer With Self Generating Reset Scheme

IP.com Disclosure Number: IPCOM000060549D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Chang, PT: AUTHOR [+4]

Abstract

This article describes a multiplexing scheme utilizing edge-triggered "flip-flops" to replace conventional level sensitive logic devices, thereby insuring greater data integrity at speeds up to 1 GHz with adequate safety margins at 500 MHz. Fig. 1 outlines a memory test system in which a 4:1 multiplexer (MUX) is employed to maintain data communications between the memory tester pattern generator and the high-speed pin electronics. The two may be separated by as much as 15 feet, creating an uncertainty as to the exact placement of any data edge and contributing to incorrect selection of data at high frequencies. Level sensitive logic gate multiplexers, such as that shown in Fig. 2, are normally used to eliminate data jitter (Fig.

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One Ghz Edge Triggered Multiplexer With Self Generating Reset Scheme

This article describes a multiplexing scheme utilizing edge-triggered "flip-flops" to replace conventional level sensitive logic devices, thereby insuring greater data integrity at speeds up to 1 GHz with adequate safety margins at 500 MHz. Fig. 1 outlines a memory test system in which a 4:1 multiplexer (MUX) is employed to maintain data communications between the memory tester pattern generator and the high-speed pin electronics. The two may be separated by as much as 15 feet, creating an uncertainty as to the exact placement of any data edge and contributing to incorrect selection of data at high frequencies. Level sensitive logic gate multiplexers, such as that shown in Fig. 2, are normally used to eliminate data jitter (Fig. 3) during data selection at 500 MHz; however, as the sampling speed increases, the sampling window shrinks. At 500 MHz, for example, the window is 8 ns (Fig. 3), with the first and last 2 ns periods containing jitter, thus contributing to erroneous readings. Only 4 ns are then left within which to place a 2 ns selection, allowing but a 1 ns safety margin on each side to accommodate any process or fabrication variation. In the disclosed multiplexer scheme, each logic gate shown in Fig. 2 is replaced by an edge- triggered "flip-flop" and data selection is done on a clock edge as opposed to a logic level selection. Fig. 4 shows a conventional collector dot master/slave "flop- flop" that must be modified for correct circuit operation. The one-input clock phase splitter (to clock master on one phase,...