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High Noise Tolerance General-Purpose Receiver Circuits

IP.com Disclosure Number: IPCOM000060551D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+4]

Abstract

This article discloses receiver circuits capable of performing from 10 to 100C, with high noise margin, under power source swings of +/- 10% of nominal voltage (5.0 v). The circuit shown in Fig. 1 features dual- phase outputs for either in-phase or out-of-phase application. In addition, transistors T6 and T9 (which can be placed in a common collector bed with T5 and T8, respectively) provide the inhibit function for the driver stage. This circuit is capable of +/- 360 mv of DC noise tolerance when operated between 10 and 100C and between 4.5 and 5.5 volts. Noise tolerance is achieved by a hysteresis input (transistors T1 and T2) and a current mirror (T3 and T4). The lower threshold is set by the sum of a Vbe (T1) and a Vsat (T3). The upper threshold is set by the ratio of resistors R2 and R3. Fig.

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High Noise Tolerance General-Purpose Receiver Circuits

This article discloses receiver circuits capable of performing from 10 to 100C, with high noise margin, under power source swings of +/- 10% of nominal voltage
(5.0 v). The circuit shown in Fig. 1 features dual- phase outputs for either in- phase or out-of-phase application. In addition, transistors T6 and T9 (which can be placed in a common collector bed with T5 and T8, respectively) provide the inhibit function for the driver stage. This circuit is capable of +/- 360 mv of DC noise tolerance when operated between 10 and 100C and between 4.5 and 5.5 volts. Noise tolerance is achieved by a hysteresis input (transistors T1 and T2) and a current mirror (T3 and T4). The lower threshold is set by the sum of a Vbe (T1) and a Vsat (T3). The upper threshold is set by the ratio of resistors R2 and R3. Fig. 2 illustrates a receiver circuit designed to accept signal voltage levels of
1.5 volts (Logic 1) and 0.6 volt (Logic 0), with which at least 350 to 400 mv of DC noise tolerance may be developed, depending upon desired circuit performance. It is composed of two parts: the receiver part and the differential part. The former includes transistors T1 and T2, diodes D1 and D2, and bias resistors Ri,_R1, Re and Rc. The latter part takes input signal A and derives A and A, as shown on the collectors of transistors T5 and T3, respectively. A high level of DC noise tolerance is obtained via the hysteresis feedback connection...