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Current Switch Read/Write Port Circuit for Multi-Port Array Cells

IP.com Disclosure Number: IPCOM000060552D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Gittleman, D: AUTHOR

Abstract

A single read/write port replaces one read port and one write port, by use of the described current switch read/write port circuit (CSRWPC), with a resultant saving in silicon and metal chip areas, i.e., a more dense chip, by the elimination of two bit lines, one word line and one resistor per read/write port. An array cell using a single CSRWPC is shown in Fig. 4. It functions in the following manner: When the word line 1 is down, and both bit lines 2 and 3 are down, the cell is being read and there is current in the resistor 4. The current is steered out of the right bit line through the right outboard transistor T4 if the array cell contains a '0'. The current is steered out of the left bit line through the left outboard transistor T1 if the cell contains a '1'.

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Current Switch Read/Write Port Circuit for Multi-Port Array Cells

A single read/write port replaces one read port and one write port, by use of the described current switch read/write port circuit (CSRWPC), with a resultant saving in silicon and metal chip areas, i.e., a more dense chip, by the elimination of two bit lines, one word line and one resistor per read/write port. An array cell using a single CSRWPC is shown in Fig. 4. It functions in the following manner: When the word line 1 is down, and both bit lines 2 and 3 are down, the cell is being read and there is current in the resistor 4. The current is steered out of the right bit line through the right outboard transistor T4 if the array cell contains a '0'. The current is steered out of the left bit line through the left outboard transistor T1 if the cell contains a '1'. When the word line 1 is down, the left bit line 2 is up and the right bit line 3 is down, the cell is being written into the '0' state and there is current in the resistor 4. The current is steered out of the left side of the cell through the left inboard transistor T2. When the word line 1 is down, the left bit line 2 is down and the right bit line 3 is up, the cell is being written into the '1' state and there is current in the resistor 4. The current is steered out of the right side of the cell through the right inboard transistor T3. When the word line 1 is up, the cell is neither being read, nor is it being written, and there is no...