Browse Prior Art Database

Cross-Coupled PNP Merged Transistor Array Cell

IP.com Disclosure Number: IPCOM000060553D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Gittleman, D: AUTHOR

Abstract

A small area storage element with low gain is described which facilitates the use of the 'merged transistor push-pull read/write port circuit' (MTPPRWPC) disclosed in the preceding article. Fig. 1 shows a low-gain storage element, the cross-coupled PNP merged transistor array cell (CCPNPMTAC), which uses the MTPPRWPC. Fig. 2 illustrates the physical implementation of the disclosed array cell in which the lateral PNP provides the low gain essential to employment of the MTPPRWPC. Fig. 3 shows a CCPNPMTAC employing two MTPPRWPCs. In this application of MTPPRWPCs, the word top line, the intermediate word line and the word bottom line can be static.

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Cross-Coupled PNP Merged Transistor Array Cell

A small area storage element with low gain is described which facilitates the use of the 'merged transistor push-pull read/write port circuit' (MTPPRWPC) disclosed in the preceding article. Fig. 1 shows a low-gain storage element, the cross-coupled PNP merged transistor array cell (CCPNPMTAC), which uses the MTPPRWPC. Fig. 2 illustrates the physical implementation of the disclosed array cell in which the lateral PNP provides the low gain essential to employment of the MTPPRWPC. Fig. 3 shows a CCPNPMTAC employing two MTPPRWPCs. In this application of MTPPRWPCs, the word top line, the intermediate word line and the word bottom line can be static.

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