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Multi-Emitter Merged Transistor Three-Port Array Cell

IP.com Disclosure Number: IPCOM000060557D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Dachtera, WR: AUTHOR [+3]

Abstract

This article concerns the design of a multiport RAM cell (2 Reads and 1 Write) allowing simultaneous read of the same memory cell and requiring a minimal chip area. Figs. 1 and 2 illustrate how a reduction in physical chip area is achieved in implementing the disclosed three-port array cell. The sense bit lines SBL1 and SBL2 are static. The two sense word line (SWL1 and SWL2) states are Down and Up. When SWL1 is Down, the cell is being read through port 1. If the cell contains a '0', the current remains in the right hand PNP transistor and there is no current in SBL1. If the cell contains a '1', the cell current is pulled out of SBL1 through the outboard emitter of the left-hand PNP transistor. When SWL2 is Down, the cell is being read through port 2.

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Multi-Emitter Merged Transistor Three-Port Array Cell

This article concerns the design of a multiport RAM cell (2 Reads and 1 Write) allowing simultaneous read of the same memory cell and requiring a minimal chip area. Figs. 1 and 2 illustrate how a reduction in physical chip area is achieved in implementing the disclosed three-port array cell. The sense bit lines SBL1 and SBL2 are static. The two sense word line (SWL1 and SWL2) states are Down and Up. When SWL1 is Down, the cell is being read through port 1. If the cell contains a '0', the current remains in the right hand PNP transistor and there is no current in SBL1. If the cell contains a '1', the cell current is pulled out of SBL1 through the outboard emitter of the left-hand PNP transistor. When SWL2 is Down, the cell is being read through port 2. If the cell contains a '0', the cell current is pulled out of SBL2 through the outboard emitter of the right-hand PNP transistor. If the cell contains a '1', the cell current remains in the left-hand PNP transistor and there is no current in SBL2. The cell can be read through port 1 and port 2 simultaneously. When SWL1 is UP, the cell is in the standby state with respect to SBL1 and does not pull any current out of it. When SWL2 is Up, the cell is in the standby state with respect to SBL2 and does not pull any current out of it. There are two states for the write word lines, UWWL and LWWL, which move together UP and Down. In the Down state, the inboard NPN transistors are two equal current sources wh...