Browse Prior Art Database

High Fan-Out Push-Pull Receiver

IP.com Disclosure Number: IPCOM000060561D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Garlett, JD: AUTHOR [+2]

Abstract

A push-pull receiver circuit featuring a low input current and a fan- out of at least 16 AND-Inverters (AIs) is described in this article. Several problems exist with high fan-out receivers for which the disclosed circuit provides a solution. The first of such problems concerns the turn-off delay (TOFF), which generally increases to unacceptable levels as the number of AIs connected to the receiver increases, due to the increased capacitance connected to the receiver input. A second problem involves the general lack of ability of a high fan-out to sink the current from its attached AI's without incurring a reliability problem.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

High Fan-Out Push-Pull Receiver

A push-pull receiver circuit featuring a low input current and a fan- out of at least 16 AND-Inverters (AIs) is described in this article. Several problems exist with high fan-out receivers for which the disclosed circuit provides a solution. The first of such problems concerns the turn-off delay (TOFF), which generally increases to unacceptable levels as the number of AIs connected to the receiver increases, due to the increased capacitance connected to the receiver input. A second problem involves the general lack of ability of a high fan-out to sink the current from its attached AI's without incurring a reliability problem. Referring to the receiver circuit shown in the drawing, the active pull-up transistor T6, as employed, reduces the TOFF (~6 nsec) significantly when compared with that obtained with other high fan-out receivers. The transistor T5, a large device, can also sink current from at least 16 AIs without reliability problems. In order to improve the noise margin of the receiver circuit illustrated, hysteresis is used via resistor R3, the schottky barrier diode S1, and the resistor R4, in combination. When the receiver input is high, the node B4 operates at approximately 0.85 volt. Since the receiver will not switch until the node B1 is about equal to B4, the receiver exhibits a nominal noise margin of 600 mvolts (350 mvolts in the worst case) in the up-level. An additional feature of this receiver circuit is its low...