Browse Prior Art Database

Basic Internal Circuit Cell Using Submicron Devices

IP.com Disclosure Number: IPCOM000060563D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR [+3]

Abstract

A particular cell layout is described which utilizes submicron field- effect transistor gates. The wiring process uses platinum areas in addition to the normal first-level wiring metal. The use of the platinum areas increases the number of first-level wiring channels. An example of one of the circuits which can be made from the cell is shown. Fig. 1 shows the basic cell layout at a stage when the wafer is partially processed. This cell forms part of an overall semiconductor chip pattern of a gate-array type. Areas 1, 2, 3 and 4 are N-pockets with the polycrystalline silicon (poly) lines 5, 6 and 7 forming the gate connections to create four N-type, MOS-type transistors 8, 9, 10 and 11 . Area 18 is a deep diffused N-well, with N-pockets 19 and 20 contained therein.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Basic Internal Circuit Cell Using Submicron Devices

A particular cell layout is described which utilizes submicron field- effect transistor gates. The wiring process uses platinum areas in addition to the normal first-level wiring metal. The use of the platinum areas increases the number of first-level wiring channels. An example of one of the circuits which can be made from the cell is shown. Fig. 1 shows the basic cell layout at a stage when the wafer is partially processed. This cell forms part of an overall semiconductor chip pattern of a gate-array type. Areas 1, 2, 3 and 4 are N- pockets with the polycrystalline silicon (poly) lines 5, 6 and 7 forming the gate connections to create four N-type, MOS-type transistors 8, 9, 10 and 11 . Area 18 is a deep diffused N-well, with N-pockets 19 and 20 contained therein. P- diffused area 21 overcomes the original N diffusion and, in conjunction with the poly lines 5, 6 and 7, forms six P-type devices 12, 13, 14, 15, 16 and 17. Area 22 which is not exposed to the P diffusion is used to make a bias connection to the N-well 18. Except for areas which have been opened up, the surface is covered with field oxide 23. N-diffused pockets 24, 25 and 26 have been formed as back-biased diodes to give excess voltage protection to the P-gate regions which are tied to the first-level metal during processing. The small squares 27 around the outside edges represent the grid coordinates for the metal wiring. It should be noted that poly lines 5, 6 and 7 are closed geometric surface shapes and are connected together electrically when initially formed....