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Reorganization System for Color Planes

IP.com Disclosure Number: IPCOM000060566D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Gohda, Y: AUTHOR [+2]

Abstract

This article describes a system which is capable of reorganizing plural color planes, i.e., memory planes for a color display. That is, n planes each of which contains X bytes can be reorganized as n/2m planes each of which contains 2m X bytes, wherein n and m are integers and (Image Omitted) The figure shows the reorganization system comprising color planes 1, 2, ... n. These planes produce outputs to respective parallel/ serial converters (PSCs) 111, 112, ... 11n which are, in turn, connected to AND gates 121, 122, ... 12n, respectively. These AND gates produce output signals C1, C2, ... Cn which are used to select one of the palette registers in a palette circuit 13. Each palette register contains color control data of p bits for controlling colors of image on a CRT color display 14. Data in the planes 1, 2, ...

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Reorganization System for Color Planes

This article describes a system which is capable of reorganizing plural color planes, i.e., memory planes for a color display. That is, n planes each of which contains X bytes can be reorganized as n/2m planes each of which contains 2m X bytes, wherein n and m are integers and

(Image Omitted)

The figure shows the reorganization system comprising color planes 1, 2, ... n. These planes produce outputs to respective parallel/ serial converters (PSCs) 111, 112, ... 11n which are, in turn, connected to AND gates 121, 122, ... 12n, respectively. These AND gates produce output signals C1, C2, ... Cn which are used to select one of the palette registers in a palette circuit 13. Each palette register contains color control data of p bits for controlling colors of image on a CRT color display 14. Data in the planes 1, 2, ... n are read out in response to an ADDRESS 1 signal on a bus 17 from a CRT controller (CRTC) 10. The CRTC 10 also issues an ADDRESS 2 signal on a bus 18 extending to a decoder 15 which also has another input from a register 16. For reorganization, a CUP (not shown) preloads via a bus 19 the register 16 with appropriate control information which designates one of possible plane configurations and controls the operation of the decoder 15 to produce decode signals D1, D2, ... Dn for controlling the AND gates 121,122, respectively. In addition, the CPU preloads the palette circuit with appropriate color control data. Assuming as an example that n=4, p=6 and each plane contains 64K bytes, the circuit 13 has to comprise sixteen palette registers each of which has a capacity of six bits. Further, the ADDRESS 1 signal has to comprise sixteen bits, i.e., AD0, ... AD15...