Browse Prior Art Database

Circuit for Expanding Display Area

IP.com Disclosure Number: IPCOM000060571D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Yamamoto, T: AUTHOR

Abstract

A circuit is disclosed which makes it possible to horizontally expand a display area of a CRT screen in graphic mode in which images (characters, graphics) are displayed using all-points-addressable (APA) memory. This circuit accesses a graphic memory dedicated to an expanded display area in horizontal retrace time using memory address signals and raster address signals output from a CRT controller. With reference to Fig. 1, a CRT controller 2 outputs memory address signals MA and raster address signals RA, shown in the upper part of Fig. 2. Address signals MA and RA are combined by a multiplexer 4 so that main graphic memory address signals MGMA, shown in the middle part of Fig. 2, are generated. The main graphic memory address signals MGMA are provided to an address input of a main graphic memory 6.

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Circuit for Expanding Display Area

A circuit is disclosed which makes it possible to horizontally expand a display area of a CRT screen in graphic mode in which images (characters, graphics) are displayed using all-points-addressable (APA) memory. This circuit accesses a graphic memory dedicated to an expanded display area in horizontal retrace time using memory address signals and raster address signals output from a CRT controller. With reference to Fig. 1, a CRT controller 2 outputs memory address signals MA and raster address signals RA, shown in the upper part of Fig. 2. Address signals MA and RA are combined by a multiplexer 4 so that main graphic memory address signals MGMA, shown in the middle part of Fig. 2, are generated. The main graphic memory address signals MGMA are provided to an address input of a main graphic memory 6. Bits 0, 1, 2, 3, 4 and 5 of MGMA correspond to an entry position, each of which consists of sixteen horizontal dots. Bits 6, 7 and 8 of MGMA correspond to a raster position of a row. Bits 9, 10, 11, 12, 13, 14 and 15 correspond to a row. Bits 9, 10, 11, 12, 13, 14 and 15 of MGMA are held by a latch 8 according to the output of AND gate 10 which receives a hold timing clock signal CLK and a display timing signal DISPTMG which is high during nonhorizontal retrace time. The reason for holding these bits is that the bits 9, 10, 11, 12, 13, 14 and 15 may designate the next row when the horizontal retrace time starts. Outputs of the latch 8 constitute b...