Browse Prior Art Database

Personalizable Ram Using a Current Steering Technique

IP.com Disclosure Number: IPCOM000060574D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Dansky, AH: AUTHOR [+2]

Abstract

This article describes the design of an efficient memory cell circuit which operates from a 1.7-volt power supply utilizing the limited active and passive components available within the internal cell area. A current steering technique is here disclosed to do the write/read operations of a standard cross-coupled flip-flop-type storage cell operating at 1.7 volts. Referring to Fig. 1, after proper conditioning of array word and bit lines, current is steered either into the cell or into the bit line. The two transistors T1 and T2 are connected as a cross-coupled latch. The four Schottky diodes D1, D2, D3 and D4 form two back-to-back (anode to anode) diode pairs.

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Personalizable Ram Using a Current Steering Technique

This article describes the design of an efficient memory cell circuit which operates from a 1.7-volt power supply utilizing the limited active and passive components available within the internal cell area. A current steering technique is here disclosed to do the write/read operations of a standard cross-coupled flip- flop-type storage cell operating at 1.7 volts. Referring to Fig. 1, after proper conditioning of array word and bit lines, current is steered either into the cell or into the bit line. The two transistors T1 and T2 are connected as a cross-coupled latch. The four Schottky diodes D1, D2, D3 and D4 form two back-to-back (anode to anode) diode pairs. The anodes of these diode pairs are connected to independent word lines WL1 and WL2, one cathode of each pair being connected to a transistor collector and the remaining diode cathodes being connected to the left and right bit lines, BLL and BLR. Referring to Fig. 2, in the Standby state, WL1 and WL2 are conditioned to a low level (approximately 0.25 volt), WL3 is conditioned to an up-level (approximately 1.7 volts), bit lines BLL and BLR are conditioned to a high impedance state by bit line bottom transistors TBL(L) and TBL(R), and the cell transistors are dotted and connected to a fixed reference. With the conditioning thus described, the cell maintains the state previously written, WL3 supplies the cell-holding current, and WL1 and WL2 (at a down level) isolate the bit lines from the memory cell by holding the bit line diodes D2 and D3 reversed biased. In the Read state (referring to Figs. 3A and 3B), the cell is read when WL1 is conditioned to an up level (approximately 1.7 volts). Current supplied from WL3 will steer through D3 or D4, depending on the present state of the memory cell. The state of the internal nodes of the transistor will be latched at 2 Vce and at Vce + Vbe (approximately 0.5 volt and 1.1 volts, respectively). The bit line is conditioned to a Vbe by the sense amplifier circuit transistor Tsen. Therefore, if the cell sense node is at 0.5 volt, then current will steer into the cell and Tsen will not have base drive and will be off. If the cell sense node is...