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Receiver Circuit With Differential Current Switch Logic Output

IP.com Disclosure Number: IPCOM000060576D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kroesen, RJ: AUTHOR [+3]

Abstract

This article concerns a receiver circuit capable of generating a well controlled dual-phase output while providing a high DC noise tolerance and a threshold independent of power supply variations (+/-10%). The receiver circuit shown in the drawing is designed to work at predetermined voltage levels and to drive a differential current switch circuit. A DC noise tolerance of at least 340-400 mv may be developed while this receiver circuit operates between 10ŒC and 100ŒC at a Vcc of 5.0 +/- 10% volts. This noise tolerance is achieved by the hysteresis feedback of transistors T1 and T2 and a current mirror of transistors T5 and T6.

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Receiver Circuit With Differential Current Switch Logic Output

This article concerns a receiver circuit capable of generating a well controlled dual-phase output while providing a high DC noise tolerance and a threshold independent of power supply variations (+/-10%). The receiver circuit shown in the drawing is designed to work at predetermined voltage levels and to drive a differential current switch circuit. A DC noise tolerance of at least 340-400 mv may be developed while this receiver circuit operates between 10OEC and 100OEC at a Vcc of 5.0 +/- 10% volts. This noise tolerance is achieved by the hysteresis feedback of transistors T1 and T2 and a current mirror of transistors T5 and T6. Threshold voltages are set by diodes D3 and D4 (down level) or by diodes D2 and D4 (up level), depending upon the transistor T3 base voltage, as determined by the states of T1 and T2 and the ratio of resistors R2, R3, and R4. Since 300 mv of voltage swing are required for up and down levels, it is necessary to limit this base voltage by using a p/n diode D2 in order to produce slightly different node voltages at node N1 while changing the states of T3 and T4. The node voltage at N1 will act to minimize the current changes in resistor R9 so that the voltage swing remains almost constant at the receiver outputs.

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