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Nmos Sense Amplifier With Automatic High Voltage Level Rewrite

IP.com Disclosure Number: IPCOM000060588D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Lee, HS: AUTHOR [+2]

Abstract

This sense amplifier (S/A) circuit, made in N channel field-effect transistor technology, eliminates bit line droop and the need for a dummy cell without having to resort to complementary metal oxide semiconductor (CMOS) technology. The S/A circuit automatically rewrites a cell to full high voltage (VH) level after a read cycle to ensure full signal storage, as well as to assure refresh and consecutive read stability. The result is a reduction in memory cycle time, reduced power dissipation, and only two columns of sense amplifiers need be activated in an interdigitated bit line dynamic random-access memory (DRAM) layout. As shown in the circuit diagram and associated timing diagram: 1) During initial sensing, the word line WL turns on first (not shown in the circuit diagram), transistors 3 and 4 are off.

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Nmos Sense Amplifier With Automatic High Voltage Level Rewrite

This sense amplifier (S/A) circuit, made in N channel field-effect transistor technology, eliminates bit line droop and the need for a dummy cell without having to resort to complementary metal oxide semiconductor (CMOS) technology. The S/A circuit automatically rewrites a cell to full high voltage (VH) level after a read cycle to ensure full signal storage, as well as to assure refresh and consecutive read stability. The result is a reduction in memory cycle time, reduced power dissipation, and only two columns of sense amplifiers need be activated in an interdigitated bit line dynamic random-access memory (DRAM) layout. As shown in the circuit diagram and associated timing diagram: 1) During initial sensing, the word line WL turns on first (not shown in the circuit diagram), transistors 3 and 4 are off. Then, after the bit line signal BC or BT is introduced to the S/A, the set pulse øs is activated to amplify the signal. Equalization of bit lines BC and BT is avoided by the presence of the depletion- mode transistors 5 and 6. Vm is the reference voltage (intermediate between zero and VH). Vm + Ws is induced on the bit line by the selected word line. 2) S/A set pulse /s initiates the regenerative/amplifying action. Since transistors 5 and 6 are depletion-mode devices and /s is boosted above VH+Vt, the bit line BT is pulled up from Vm level to VH level. Thus, a full VH level is rewritten back to the m...