Browse Prior Art Database

High Performance 32-Bit Shifter in CMOS Technology

IP.com Disclosure Number: IPCOM000060591D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A technique is described whereby a particular CMOS gate array circuit library is used to perform single 16-bit or 32-bit double left circular, right arithmetic and left logical shifts of various amounts. Also, the concept provides the ability to complement the input data value with only four levels of circuit delay to realize all functions. Many CMOS technology circuit families do not provide wired OR capability. The largest CMOS AND/OR circuit family provides for a maximum of four groups of inputs with a maximum of two inputs in each group. This allows, at most, a four-way multiplexer to be utilized in one stage of delay on a single output signal line.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

High Performance 32-Bit Shifter in CMOS Technology

A technique is described whereby a particular CMOS gate array circuit library is used to perform single 16-bit or 32-bit double left circular, right arithmetic and left logical shifts of various amounts. Also, the concept provides the ability to complement the input data value with only four levels of circuit delay to realize all functions. Many CMOS technology circuit families do not provide wired OR capability. The largest CMOS AND/OR circuit family provides for a maximum of four groups of inputs with a maximum of two inputs in each group. This allows, at most, a four-way multiplexer to be utilized in one stage of delay on a single output signal line. The concept is unique in that the shifter has the ability to handle both single and double word shifts when performing shift left circular, shift left logical and shift right arithmetic. It has the ability to perform the complement input function in only four stages of delay, in a technology where wired OR capabilities are prohibited or where there is a restrictive circuit library. The shifter shifts only in one direction (right). However, it handles left shifts as well in the following manner: If a data word is shifted to the right, the data from each bit "n" is shifted right the specified number of positions "p", and its value now becomes the value of output bit "n+p". To perform a left shift, the B register data source is placed in the shifter in reverse order so that by shifting right, the data shifts towards the low end bit, effectively shifting left. The final stage of the shifter then reverses the order of the bits in the result so that the data is ordered back to the original, the same as if a right shift had been performed. The logical concept of the shifts is shown in Fig. 1 with the functions performed at each stage. Stage 1, as shown in Fig. 2, shows the first stage of each shifter and the input bit (B register) that would be gated to each output bit for the twelve possible combinations of shifts to be performed at this level. For example, a double right arithmetic shift would put Bit 0 of the B register on the output of Stage 1, Bit 0, while a single word circular shift left 1 would put B register 16 on the output of Stage 1, Bit 0. Fig. 3 shows the twenty combinations of shifts and the Stage 1 output bits that will appear on the output of each Stage 2 bit for each of the twenty shift combinations. Note that nine of the...