Browse Prior Art Database

Checking of Error Correction Code (ecc) Corrected Data

IP.com Disclosure Number: IPCOM000060613D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kienzle, TC: AUTHOR [+3]

Abstract

This circuit detects a false or failed data correction.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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Checking of Error Correction Code (ecc) Corrected Data

This circuit detects a false or failed data correction.

ECC system 10 checks the ECC codeword from source registers 12 and then corrects any single bit errors encountered. Failure of the ECC system to properly correct bad data can produce later problems without any reasonable method to trace the failing element. To prevent this problem, parity is generated by parity generators 14 for each four bits of the codeword. The resultant data registers 16 are then examined for parity errors by correction check circuit 18 after the data correction by the ECC sy 10. If the ECC checker 10 indicates that there is a multibit error or no error in the source registers 12, the parities in the resultant register's parities should be correct. If a single bit error is detected in the source register by the ECC system 10, then exactly one resultant register parity error is expected.

Disclosed anonymously.

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