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Browse Prior Art Database

Optical Isolation Trench

IP.com Disclosure Number: IPCOM000060630D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Sun, YC: AUTHOR

Abstract

This article relates generally to integrated circuit storage cells and, more particularly, to cell isolation.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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Optical Isolation Trench

This article relates generally to integrated circuit storage cells and, more particularly, to cell isolation.

Storage cell holding time in silicon dynamic random access memory chips can be extended by filling isolation trenches with photon-absorbing material, such as germanium. The trenches can be fabricated in the conventional manner and filled by chemical vapor deposition of polycrystalline germanium. Minimum trench width should be at least two microns and, after trench filling, further processing temperatures are kept below the 937OEC melting point of the germanium.

This type of trench can be used to selectively enclose peripheral circuits and allow operation at higher voltages. Any semiconductor can be used for the trenches that is capable of large absorption of photons having energies greater than 1.1eV and is compatible with silicon VLSI processes. The optical isolation prevents the degradation of holding time due to excess minority carriers generated by photons or due to the generation of photons at forward-biased p/n junctions.

This approach is particularly effective in n-well CMOS dRAM with p-channel arrays where the holding time is susceptible to degradation due to excess minority carriers generated by photons.

Disclosed anonymously.

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