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Process for Making a Two-Device Non-Destructive Read-Out Memory Cell in a Three-Dimensional Structure

IP.com Disclosure Number: IPCOM000060704D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Landler, PF: AUTHOR

Abstract

A process is described which utilizes trench structure and processing to build a non-destructive read-out (NDRO) memory cell comprised of one p-type transistor, one n-type transistor and a capacitor. The process results in utilization of three dimensions for transistor construction, minimizing the amount of surface area required for the cell. The circuit shown in Fig. 1 is the final product of the process to be described. The bit line B/L is connected to the source of transistor T2 (p-type) and to the source of transistor T1 (n-type). The gate of transistor T2 is connected to the write enable line W/E. The drain of transistor T2 is connected to the gate of transistor T1 and to the upper plate of capacitor C. The word line W/L is connected to the lower plate of capacitor C and to the drain of transistor T1.

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Process for Making a Two-Device Non-Destructive Read-Out Memory Cell in a Three-Dimensional Structure

A process is described which utilizes trench structure and processing to build a non-destructive read-out (NDRO) memory cell comprised of one p-type transistor, one n-type transistor and a capacitor. The process results in utilization of three dimensions for transistor construction, minimizing the amount of surface area required for the cell. The circuit shown in Fig. 1 is the final product of the process to be described. The bit line B/L is connected to the source of transistor T2 (p-type) and to the source of transistor T1 (n-type). The gate of transistor T2 is connected to the write enable line W/E. The drain of transistor T2 is connected to the gate of transistor T1 and to the upper plate of capacitor C. The word line W/L is connected to the lower plate of capacitor C and to the drain of transistor T1. The process to be described (referencing Figs. 1, 2 and 3) creates the cell circuit of Fig. 1, as shown in cross section in Fig. 3. First, referring to Fig. 2, a trench W is etched in a p- substrate along the word line direction. A gate oxide 4 is grown on the exposed silicon, and an n+ layer 6 formed in the horizontal surfaces of the substrate by ion implantation. A p+ polysilicon 16 is deposited and is etched so that it remains only in the trench W. A mask is then used to define and subsequently etch a narrow trench N through the polysilicon 16 and through the bottom of the trench W. Silicon dioxide (SiO2) 10 is deposited by chemical vapor deposition (CVD), followed by a directional etch, e.g., reactive ion etch (RIE). An n- polysilicon layer 12 is...