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Two-Pass Stuck-Fault Memory Test Error Correction Code

IP.com Disclosure Number: IPCOM000060707D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Finlay, DE: AUTHOR [+4]

Abstract

This is a description of a modification of a standard Hamming code which minimizes the time that is needed to test a memory with Error Correction Code (ECC) for bits stuck at 1 and at 0. Many present memory card designs use a 'standard version' of a modified Hamming code, and therefore require a three-pass memory test. This ECC bit arrangement would only require a two-pass memory test to test for stuck memory bits. The previous implementation would yield the same ECC bits for exactly complementary data in the 16-bit data word.

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Two-Pass Stuck-Fault Memory Test Error Correction Code

This is a description of a modification of a standard Hamming code which minimizes the time that is needed to test a memory with Error Correction Code (ECC) for bits stuck at 1 and at 0. Many present memory card designs use a 'standard version' of a modified Hamming code, and therefore require a three- pass memory test. This ECC bit arrangement would only require a two-pass memory test to test for stuck memory bits. The previous implementation would yield the same ECC bits for exactly complementary data in the 16-bit data word.

This implementation yields complementary ECC bits for complementary data bits, therefore making a two-pass test possible. Table #1 shows an example of a 22-bit modified Hamming error correction code used on memory card designs which use a 'standard' version of a modified Hamming code. Check bits are generated using either table #1 or #2 as follows: 1. Line up the halfword of data under the ECC bit generation chart. 2. If the number of columns where the XX's in the table and '1's in the data coincide is an odd number for a check bit row, set each appropriate check bit to a '1'. Since, in the 'standard' design, the number of X's in each ECC bit row is an even number, complementary data will either yield two odd or two even counts for ECC bit generation and therefore yield the same ECC bits. In the new design, since the number of X's in each ECC bit row is an odd number, complementary data will yield one odd and one even count for ECC bit generation and therefore yield complementary ECC...