Browse Prior Art Database

Stackable "J" Leaded Chip Carrier

IP.com Disclosure Number: IPCOM000060709D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Mullady, RK: AUTHOR

Abstract

This design provides molded-in features that permit "J" leaded chip carriers to be stacked. This increases packaging density and is especially useful in memory applications. The design differs from that presented in [*] in that in this design top and bottom packages are identical. There are no special lead form requirements and no unique bosses on either package. Either package can be used by itself or in a stacked configuration. In the showing of the figure, corresponding parts of the lower and upper packages are given the same reference number, except that the upper package members are primed. As shown, die 10, around which each lead 12 is formed, is chamfered (as seen at 14) and the dies 10' of the upper package 16 rest in a corresponding chamfered notch 18 provided in the top of the lower carrier 20.

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Stackable "J" Leaded Chip Carrier

This design provides molded-in features that permit "J" leaded chip carriers to be stacked. This increases packaging density and is especially useful in memory applications. The design differs from that presented in [*] in that in this design top and bottom packages are identical. There are no special lead form requirements and no unique bosses on either package. Either package can be used by itself or in a stacked configuration. In the showing of the figure, corresponding parts of the lower and upper packages are given the same reference number, except that the upper package members are primed. As shown, die 10, around which each lead 12 is formed, is chamfered (as seen at 14) and the dies 10' of the upper package 16 rest in a corresponding chamfered notch 18 provided in the top of the lower carrier 20. This provides both x and y alignment of the two carriers. The flaring 22 of the lead 12 provides a large pad 24 for the upper lead 12' to attach to. This not only helps alignment for skewed leads, but also provides for a good solder fillet 26, as shown in Detail A. The attachment process would be similar to that in [*]. Reference [*] P. V. Robock, "Stackable Plastic Semiconductor Chip Carrier," IBM Technical Disclosure Bulletin 27, 2389 (September 1984).

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