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Browse Prior Art Database

Integrated Schottky Diode in CMOS

IP.com Disclosure Number: IPCOM000060711D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Hargrove, M: AUTHOR [+4]

Abstract

An integrated Schottky barrier diode (SBD) is created in either the source or drain diffusion of an n-channel metal oxide semiconductor field-effect transistor (MOSFET). No additional masking step is required. The integrated SBD is formed by conventional processing through definition of the polysilicon gate lines 2, as shown in Fig. 1. An arsenic (As) ion beam exposure of the entire wafer results in the lightly doped, n- implanted regions 4 and 6. The region 6 ultimately becomes the SBD or lightly doped drain region. Following subsequent conventional processing, i.e., spacer 8 definition, a blocking mask 10 protects the lightly doped drain region 6 (as well as any p-channel device regions) while the source region 4 is highly doped (n+) by another As ion implant, as shown in Fig. 2.

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Integrated Schottky Diode in CMOS

An integrated Schottky barrier diode (SBD) is created in either the source or drain diffusion of an n-channel metal oxide semiconductor field-effect transistor (MOSFET). No additional masking step is required. The integrated SBD is formed by conventional processing through definition of the polysilicon gate lines 2, as shown in Fig. 1. An arsenic (As) ion beam exposure of the entire wafer results in the lightly doped, n- implanted regions 4 and 6. The region 6 ultimately becomes the SBD or lightly doped drain region. Following subsequent conventional processing, i.e., spacer 8 definition, a blocking mask 10 protects the lightly doped drain region 6 (as well as any p-channel device regions) while the source region 4 is highly doped (n+) by another As ion implant, as shown in Fig.
2. Conventional processing steps comprised of insulator 12 deposition, source and drain via hole etching, and formation of metal lines 14, 16, 18 result in the structure shown in Fig. 3. The intimate contact of the metal line 14 to the lightly doped drain region 6 forms the integrated SBD. The diode thus formed may be used to avoid unwanted circuit paths. This results in power reduction, latch-up avoidance, and/or higher circuit performance for CMOS circuits.

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