Browse Prior Art Database

Fast 32-Bit Arithmetic Logic Unit in CMOS Technology

IP.com Disclosure Number: IPCOM000060726D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A technique is described whereby a fast 32-bit ALU (Arithmetic Logic Unit) is designed using CMOS technology so that only four stages of delay are experienced to obtain the carry out of the adder and that all sums have a maximum of six stages of delay. Many versions of CMOS circuitry do not provide wired OR capability and the circuit library is limited. Performance is usually determined by the stages of delay in a circuit path plus loading on the circuit networks. By reducing the loading requirements, performance can be substantially increased. The concept described herein provides a 32- bit ALU with only four loads on the input data bits and three loads on the group carries. The individual sum logic does not use any AND/OR circuits with four input groups.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Fast 32-Bit Arithmetic Logic Unit in CMOS Technology

A technique is described whereby a fast 32-bit ALU (Arithmetic Logic Unit) is designed using CMOS technology so that only four stages of delay are experienced to obtain the carry out of the adder and that all sums have a maximum of six stages of delay. Many versions of CMOS circuitry do not provide wired OR capability and the circuit library is limited. Performance is usually determined by the stages of delay in a circuit path plus loading on the circuit networks. By reducing the loading requirements, performance can be substantially increased. The concept described herein provides a 32- bit ALU with only four loads on the input data bits and three loads on the group carries. The individual sum logic does not use any AND/OR circuits with four input groups. The ALU requires only 278 CMOS circuit cells to generate the 32-bit carry with only four stages of delay and provides all sums with six or less stages of delay. The ALU block diagram in Fig. 1 shows the data and control inputs along with the outputs. The A and B inputs are of negative polarity, but could be of positive polarity with an added delay of approximately 1.5 ns. The outputs are of positive polarity, but could be negative by changing the output XOR circuits, as shown in Fig. 5, to XNOR circuits. The typical four-bit group with the AND of the four-bit pairs, the group carry and the group propagate are shown in Fig. 2. The AND of each bit pair is done in one stage of delay while the group carry and group propagates are two stages of delay. Bits 5-7 provide the three...